New Course Bridges Industry Gap in Hardware Verification

As computer chips grow more complex, designing hardware is only part of the challenge. Ensuring that those designs work correctly has become one of the most critical and in-demand skills in the semiconductor industry. To address this need, Carnegie Mellon’s Department of Electrical and Computer Engineering has introduced a new course: Hardware Verification.

The course responds directly to long-standing feedback from industry partners who have emphasized a growing gap in undergraduate and graduate curricula: while students are well trained in circuit design, few receive formal education in how to systematically verify modern hardware designs.

“We are very good at teaching students how to design circuits and make them fabrication-ready,” said Sam Pagliarini, special professor of electrical and computer engineering, and who developed and teaches the course. “However, modern computer chips are extremely complex, with features built on top of features. It is not trivial to verify that every intended feature is present in the chip, or that the interactions between features are correctly implemented.”

Hardware Verification introduces students to the principles and practices used by verification engineers in industry. Students learn how to write effective SystemVerilog testbenches that exercise designs and expose corner cases through simulation. A core component of the course is the Universal Verification Methodology (UVM), the industry-standard framework for organizing and scaling verification environments.

In addition to simulation-based verification, students are exposed to verification metrics that help quantify confidence in a design’s correctness, as well as elements of formal verification using SystemVerilog Assertions. The course also introduces related topics such as linting, non-functional verification, analog and physical verification, and verification management, providing students with a broad view of the verification landscape.

The course was developed with input from an industry leader and refined through extensive collaboration with teaching assistants prior to its first offering in the fall of 2025. The goal was to ensure that the content reflects how verification is practiced in real engineering environments.

“As a general rule of thumb, there is a higher demand for jobs in circuit verification than in circuit design,” says Pagliarini. “Industry benefits from having a pool of highly talented graduates who already understand the inner workings of a verification methodology. This course helps students enter those roles ready to contribute from day one.”

The course emphasizes hands-on learning. Students spend more time in the lab than in lecture, working directly with tools and methodologies used in industry. The course culminates in a comprehensive final project in which students are given a hardware design and a natural-language specification that may be ambiguous or incomplete, mirroring real-world conditions. Students must then interpret the specification, develop a verification plan, and create tests to demonstrate whether the design’s features are implemented correctly. Uniquely, students are allowed to present their final project multiple times, incorporating feedback, and refining their work over the course of the semester.

“As long as students are making progress, they can improve their grades by presenting again,” says Pagliarini. “Most students end up presenting about three times in order to secure an A on the final project.”

For students, the course provides both technical depth and career clarity. Sutong Yao, a senior in electrical and computer engineering who completed the course last semester, enrolled to gain formal training in verification and UVM, skills she knew were essential but rarely taught in universities.

“The course covered the fundamentals of verification and how to build a complete UVM-based verification project,” says Yao. “We also interacted with a startup working on AI-based verification and heard from guest speakers who are leaders in the field.”

Yao credits the course with helping her stand out in job interviews and internships, where many engineers typically need additional internal training to learn verification methodologies.

“This course was extremely helpful for my career,” she said. “It also solidified my decision to pursue a career as a hardware verification engineer.”

By introducing students to verification methodologies used in practice, Hardware Verification closes a critical gap in the electrical and computer engineering curriculum. The course equips students with skills that are in high demand across the semiconductor industry while providing a realistic, hands-on educational experience.

As hardware systems continue to increase in scale and complexity, the ability to verify them effectively is no longer optional, it is essential. This new course ensures that students are prepared to meet that challenge.