Cadence University Program
CMU is a Cadence University Program Member
Cadence design tools are used in a variety of undergraduate and graduate classes to provide practical experience in the design of integrated circuits and systems. Additionally, they are used by several research groups in the design of chips integrating
Policies
Cadence design tools are available for use by all students, staff and post-docs that are active in academic and research activities in ECE. Others who desire access must contact help@ece.cmu.edu first.
- Benchmark studies of the software tools
is expressly forbidden. - Cadence supported documentation must not be copied from the Cadence AFS tree to user directories.
- For additional help, manuals, training and expert questions please ask the students, TAs and professors who teach the courses listed below or who are affiliated with the research labs listed below.
Students and researchers wishing to access the Cadence support site need to contact help@ece.cmu.edu. When requesting access Cadence requires the following:
- Your full name
- Your CMU email address
- Your phone number
Individuals requesting access need to review and agree to the Terms of Use Agreement found at [1]. Access is renewed annually at the time of our license renewal, typically July of each year. Please note, this provides access to the knowledge base but does not allow for the user to download software or open support tickets with Cadence. Requests for software updates and support tickets must be submitted through help@ece.cmu.edu.
Tools
Only Cadence products are listed in this page. For other CAD tools or other products visit the applications page in this wiki.
- Allegro
- ICFB (Front to Back Design Environment)
- SpectreMDL (scripting language)
- Encounter (place and route)
Classes
- 18-310
- Fundamentals of Semiconductor Devices
- This class introduces the student to the operation and fabrication of commonly used integrated circuit devices such as the diode, the bipolar junction transistor and the MOS transistor. Some of the labs in this class are based on the circuit simulation tools within the Cadence Custom IC tool suite.
- 18-320
- Microelectronic Circuits
- This class introduces the students to basic microelectronic circuits, how they are fabricated, the basic devices which are used to build circuits and how to analyze both analog and digital circuits. The labs in the class are design oriented, utilizing schematic entry and simulation using tools from the Cadence Custom IC tool suite.
- 18-421
- Analysis and Design of Analog Circuits
- This class develops the student's ability to analyze circuits that include ideal and non-ideal operational amplifiers, diodes, bipolar junction transistors and MOS transistors. The labs in the class are design oriented, and schematic entry and simulation are critical steps to completing the labs in time. The lab manuals which describe the use of the Cadence Custom IC tools can be found by logging into Blackboard and entering the Guest Users section.
- 18-422
- Analysis and Design of Digital Circuits
- This class develops the student's ability to design a small chip using both synthesis-based and custom design flows, and involves circuit simulation with Spectre, logic simulation with Verilog, and layout generation with Virtuoso. An excellent lab manual is maintained by the TA's.
- 18-447
- Introduction to Computer Architecture
- This class develops the student's ability to design and simulate register-transfer-level models of superscalar architectures using Verilog.
- 18-622
- Advanced Digital Integrated Circuit Design
- This class focuses on the design of high-performance digital CMOS circuits. Students use Cadence's custom design flows, including transistor-level circuit simulation with Spectre, logic simulation with Verilog, layout generation with Virtuoso and extraction with Assura.
- 18-623
- Analog Integrated Circuit Design
- This class develops the student's ability to design analog integrated circuits through several design problems. The class uses the Cadence generic physical design kit, schematic composition in Composer, netlisting with the Analog Design Environment, circuit simulation with Spectre, and layout generation with Virtuoso and NeoCell. The lab manuals can be found by logging into Blackboard and entering the Guest Users section.
- 18-723
- RFIC Design and Implementation
- This class focuses on the design techniques for the analog circuits interfacing between digital systems and the real world. The focus of the class over the years has included data converters, switched capacitor filters, and digital communications channels. Practical design experience is developed through several paper design projects that use Composer, Analog Design Environment, Spectre and SpectreRF. Additional information can be found at the Blackboard web site.
- 18-725
- Advanced Digital Integrated Circuit Design
- This class covers the design process of VLSI CMOS circuits in nanoscale technologies. All the major steps in the design process, which include system, logic, circuit and layout design are covered. Cadence tools are used in the class and augmented with tools developed by CMU graduate students. One or more of the completed projects will be submitted for fabrication.
- 18-765
- Digital Systems Testing and Testable Design
- This class examines the theory and practice of fault analysis, test generation and design for testability in digital ICs and systems. Cadence test tools such as the Encounter platform are used in the homework and projects in this course.
Research
Several research thrusts within the Center for Silicon System Implementation routinely use the Cadence design tools for taping out chips to silicon foundries. Listed below are links to some of the internal web pages regarding the Cadence design tools maintained by these groups:
- The Digital Sandbox sustains a hands-on laboratory environment for the Pittsburgh Digital Greenhouse Education and Training programs for students at Carnegie Mellon, U. Pittsburgh and Penn State. Its reference flow includes Cadence tools such as NC-Verilog, Virtuoso-XL.
- The MEMS Lab maintains a detailed set of tutorial pages for the use of Cadence in
analog , RF and MEMS circuit design. The lab also focuses onbehavioral modeling for MEMS design using Cadence tools as part ofa NSF supportedproject on "Building a Virtual Micro/Nanosystems Design Community". - The VPGA Project maintains a restricted web page to its design flow.
Known Problems & Solutions
The Cadence FAQ may be a good place to start.
GLIBC_2.0 not defined in file libc.so.6
Affected versions: All versions
Affected DKs: All
Affected OS: Suse 9.3
Summary: When starting Cadence the following error appears "/usr/cds/ic-5.0/tools/dfII/bin/icfb.exe: relocation error: /usr/cds/ic-5.0/tools/dfII/bin/icfb.exe: symbol
If using tcsh shell, setenv LD_ASSUME_KERNEL 2.4.1 If using bash shell, LD_ASSUME_KERNEL=2.4.1; export LD_ASSSUME_KERNEL
opusdbtype
Affected versions: All
Affected DKs: st065 v3.0
Affected OS: All
Summary: When starting Cadence the following error appears "Mandatory Shell Environment Variable
If using tcsh shell, setenv opusdbtype If using bash shell, opusdbtype=""; export opusdbtype
Lost in file system
Affected Versions: All
Affected DKs: All
Affected OS: Suse 9.3
Summary: When starting Cadence, the software reports an error message "Lost in
fs sa . system:anyuser l
Cadence Start Up Scripts
Getting a Cadence tool to start typically involves setting several environment variables and then launching the tool. Many of the legacy scripts in ECE were developed in
If you are unfamiliar with basic UNIX shell scripting we recommend that you
There are many online resources that cover the basics of shell scripting. Below is a short list:
- bash
csh
Example Script
# variables that are common to most instances # location of the Cadence License export LM_LICENSE_FILE=5280@cadence-lic.ece.cmu.edu # specify that the tool should run in 64 bit mode export CDS_AUTO_64BIT=ALL # create a variable to hold the path to the top level directory # for your tool. This allows you to update other parts of the script # simply by changing single variable export CDSHOME=/afs/ece/support/cds/share/image/usr/cds/ic-6.17.710 # add the tool to your PATH export PATH=$CDSHOME/tools/bin:$CDSHOME/tools/dfII/bin:$PATH # we would like to use assura as part of this session # by setting ASSURAHOME and adding ASSURA to our PATH that option # should be enabled in the virtuoso menu export ASSURAHOME=/afs/ece/support/cds/share/image/usr/cds/assura-4.15.001-617 export PATH=$PATH:$ASSURAHOME/tools/assura/bin # start the tool virtuoso
Additional Considerations
Cadence is a suite of tools that can be changed used either individually or together. Some of the more specialized tools will have additional environment variables that need to be set or considered when creating your script.
Additionally, as updates happen within the ECE environment some tools may need some helper variables added to enable them to function. An example of this happened when we moved from SuSE to RHEL6 or from RHEL6 to RHEL7. During
For example, when we migrated to RHEL6 the version of IC that was commonly in use, ic-6.16.090, did not have support for anything beyond RHEL5. Typically tools will still function correctly with a newer operating system but need to be told which library to use. This can be done by overriding the search for the OA version and specifying it:
export OA_UNSUPPORTED_PLAT=linux_rhel50_gcc44
OA_UNSUPPORTED_PLAT tells the tool to use the version of OA specified, in this case linux_rhel50_gcc44, if it cannot determine which version to use in the standard way.
This is just one example of an additional environment variable. There are many that can be put to use and they are typically described in the tool documentation.
Cadence is a registered trademark of Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134.