The Digital Twin That Could Keep AI Chips Cool

For years, the semiconductor industry has been obsessed with packing more transistors into smaller spaces. As the AI boom drives demand for increasingly powerful processors, a less glamorous problem is becoming impossible to ignore: heat.

Modern computer chips are no longer single layers of silicon. Instead, they are built from chiplets, or smaller specialized chips stitched together into a single package. While this modular approach allows manufacturers to mix and match components, it creates a maze of pathways that heat could flow through, making it impossible to predict its route.

A research team from Carnegie Mellon’s Department of Electrical and Computer Engineering believes the solution could be to build a thermal digital twin of every chip system.

Atharva Raut of the NEXUS Research Group and Je-Wei Chuang of the Advanced Chip Test Laboratory, both current Ph.D. students in electrical and computer engineering, have received the prestigious 2026 Qualcomm Innovation Fellowship for their proposal, “Test-Calibrated Thermal Digital Twins for Chiplet 2.5D/3D SoCs”.

A well-known concept in manufacturing industries, digital twins are virtual replicas of physical systems that can predict behavior before problems occur. When applied to semiconductors, a thermal digital twin would create a living model of how heat actually moves through a specific chip package, rather than how engineers assume it should move on paper.

“Thermal behavior is difficult to predict accurately because of the complex and non-ideal heat-flow paths across the die, interposer, package, and cooling stack,” explains Raut. “A more accurate thermal twin could help designers identify hotspots before they become failures, optimize cooling systems, reduce energy consumption, and safely extract more performance from advanced processors.”

The proposed work aims to develop a test-calibrated thermal digital twin that combines compact thermal modeling, structured thermal excitation during test, on-chip sensor measurements, and lightweight machine-learning correction to capture silicon- and package-specific variation.

“It represents an exciting first step toward more accurate, silicon-aware thermal modeling for future chiplet-based systems,” says Chuang. “Our goal is to create a thermal digital twin that doesn't just represent an ideal design, it reflects the unique characteristics of the actual chip and package.”

While the project is still in its early stages, it points toward a future where chips may come with something more than transistors and circuits: a digital counterpart that continuously understands how the hardware behaves in the real world.

Every year, Qualcomm selects a limited number of researchers to receive their Innovation Fellowship, an award that promotes the company’s core values of innovation, execution, and teamwork. The 2026 cohort was one of the most competitive in the award’s history, with just a 4% acceptance rate (16 of 392 teams).

The work is advised by Tathagata Srimani, assistant professor of electrical and computer engineering, and Shawn Blanton, the Joseph F. and Nancy Keithley Professor of Electrical and Computer Engineering.