The Fourth Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL 2015)

Portland, Oregon - Sunday, June 14, 2015

Oregon Convention Center, Room D-132

Co-located with ISCA 2015

Archived CARL 2012 Contents

The Second Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL 2012), Portland, Oregon - Sunday, June 10, 2012 Co-located with ISCA-39

The Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL) is a new forum for presenting FPGA and reconfigurable logic research relevant to a computer architecture audience. In recent years, there has been a renewed interest in reconfigurable computing, driven by the need for greater computing performance and, at the same time, better power and energy efficiency. Reconfigurable computing is a key technology candidate to efficiently leverage exponential device scaling beyond current multicore processors.

This full-day workshop will be held on Sunday, June 10, 2012, co-located with ISCA-39 in Portland, Oregon.

Program of Invited Presentations

Two categories of submissions were solicited for review, (1) new unpublished manuscripts and (2) audience-appropriate revisions of papers already published or under review outside of traditional computer architecture forums. (See Call for Papers below.) Each 4~6-page submission was assigned to 4~5 members of the program committee for review. At the end, the program committee invited 7 out of the 12 submitted papers for presentation at the CARL Workshop. (Submissions selected for presentation at CARL are not published.) In addition, the program include a keynote presentation by Jason Cong (UCLA) and invited industry talks on Intel QPI-FPGA by Neal Oliver (Intel) and ArchES MPI by Paul Chow (U of Toronto).

  • 7:00-9:00 Conference Breakfast
  • 8:45-10:00 Keynote
    • Welcome, Derek Chiou, Joel Emer and James C. Hoe
    • Era of Customization and Specialization, Jason Cong, UCLA (www)
  • 10:00-10:30 Morning Break (refreshment provided)
  • 10:30-12:00 Architecture and Abstractions for Computing (Chair: John Davis, MSR)
    • VENICE: A Compact Vector Processor for FPGA Applications, Aaron Severance, University of British Columbia; Guy Lemieux, University of British Columbia (PDF, slides)
    • A Coarse-Grain FPGA Overlay for Executing Data Flow Graphs, Davor Capalija, University of Toronto; Tarek Abdelrahman, University of Toronto (PDF, slides)
    • Extending Course-Grained Reconfigurable Arrays with Multi-Kernel Dataflow, Robin Panda, Aaron Wood, Nathaniel McVicar, Carl Ebeling, Scott Hauck, University of Washington (PDF)
  • 12:00-1:30 Conference Lunch
  • 1:30-2:30 Invited Industry Talks
    • QPI-FPGA Platform for Prototyping Cache Coherent Reconfigurable Systems, Neal Oliver, Intel (slides)
    • MPI as a Programming Model and Development Environment for Heterogeneous Computing, Paul Chow, U of Toronto/ArchES (slides)
  • 2:30-3:30 Tools and Infrastructures (Chair: Eric Chung, MSR)
    • Heracles 2.0: A Tool for Design Space Exploration of Multi/Many-core Processors, Michel Kinsy, MIT; Srini Devadas, MIT (PDF, www)
    • CONNECT: Fast Flexible FPGA-Tuned Networks-on-Chip, Michael Papamichael, Carnegie Mellon University; James Hoe, Carnegie Mellon University (PDF,slides, www)
  • 3:30-4:00 Afternoon Break (refreshment available until 3:45)
  • 4:00-5:00 Applications in Computing (Chair: Kees Vissers, Xilinx)
    • A Stall-Free Real-Time Garbage Collector for FPGAs, David Bacon, IBM; Perry Cheng, IBM; Sunil Shukla, IBM (PDF, slides, www)
    • An FPGA Drop-In Replacement for Universal Matrix-Vector Multiplication, Eric Chung, Microsoft Research; John Davis, Microsoft Research; Srinidhi Kestur, The Pennsylvania State University (PDF, slides)
  • 5:00-5:30 Quick Pitches
    • FaBRIC: Community FPGA Cloud, Derek Chiou, UT Austin
    • The Elan Programming Model for Configurable Computing - Recent Results, Carl Ebeling, University of Washington

Call for Papers

(Call for Papers)

Research Papers. We invite research papers from all areas of FPGA and reconfigurable logic that impact the computer architecture community. Major areas of interests include, but are not limited to:

  • New FPGA architectures and reconfigurable fabric designed to support computing
  • Heterogeneous computing processors and systems that incorporate reconfigurable logic
  • Computation models and programming tools for reconfigurable and heterogeneous computing
  • State-of-the-art (ready-for-use) reconfigurable computing platforms and infrastructure
  • Algorithms and applications for reconfigurable computing (including FPGA-based prototyping and simulation of computer systems)
  • Evaluations of reconfigurable computing in terms of performance, power/energy, flexibility and cost, especially in comparison to other hardware paradigms (multicore, GPU, ASICs, etc.).

We will accept submissions in two categories: (1) new unpublished manuscripts, and (2) audience-appropriate revisions of papers already published or under review outside of traditional computer architecture forums (ISCA, MICRO, HPCA, PACT, etc.). Papers selected for presentations will not be published in any formal proceedings.

A submission should be 4~6 pages in double-column format. The review process is not blind; please include authors' names and affiliations. Please clearly indicate whether a submission is category 1 or 2 in the header area of the submission. If category 2, the source materials must be explicitly introduced in both the abstract and introduction.

Quick Pitches. In addition to formal research presentations, CARL 2012 will have a “quick-pitch” session for short 8-minute informal presentations to pitch a new idea, make an announcement, etc. The presenter's goal is to engage the CARL audience so they will want to find out more from a website. Interested presenters should submit a 1-page proposal that includes a title; presenter's name and affiliation; an abstract of the presentation; and a web-link to the website being pitched. Preference will be given to topics that are current and has a broad appeal to the CARL audience.

Questions? Please email questions about this Call-for-Papers to

Submission Site

Please submit your paper and quick-pitch proposal through the submission site before March 30, 2012. (We like to thank Microsoft Research for this service.) If you encounter any problems with your submission, please email

Important Dates

  • Paper and Quick-Pitch Submission Deadline: Friday, March 30, 2012
  • Notification of Selection: Monday, April 30, 2012
  • Final Paper Submission: Monday, May 28, 2012
  • Workshop: June 10, 2012

Technical Program Committee

  • Dave Albonesi, Cornell University
  • Vaughn Betz, University of Toronto
  • John Davis, Microsoft Research
  • Srini Devadas, MIT
  • Carl Ebeling, University of Washington
  • Shih-Lien Lu, Intel
  • Robert Mullins, University of Cambridge
  • David Penry, Brigham Young University
  • Vijay Reddi, University of Texas, Austin
  • Graham Schelle, Xilinx
  • Sunil Shukla, IBM
  • Satnam Singh, Google
  • Chuck Thacker, Microsoft Research
  • Kees Vissers, Xilinx
  • Tao Wang, Peking University
  • John Wawrzynek, UC Berkeley