This area focuses on tools and design methodologies for modeling, analysis, and optimization of critical design constraints (performance, power, reliability, etc.) at the system and architecture level. With the increased need for addressing challenges due to more on-chip complexity, communication and power costs, and design variability, new design aids are essential very early in the design process. Research in this area targets scalable performance, power and reliability modeling, and associated novel design paradigms for dealing with on-chip communication, power management, and variability-aware design.

Area Leader

Diana Marculescu


  1. Shawn Blanton
  2. Gary Fedder
  3. Pulkit Grover
  4. James Hoe
  5. Ken Mai
  6. Diana Marculescu
  7. Radu Marculescu
  8. Tamal Mukherjee
  9. Larry Pileggi
  10. Don Thomas

2012 Research Summaries