• B. Calhoun, X. Li, K. Mai, L. Pileggi, R. Rutenbar, K. Shepard, “Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS” To appear in Proceedings of the IEEE. (In press)
•E. Chung, E. Nurvitadhi, J. Hoe, K. Mai, B. Falsaﬁ, “Accelerating Architectural-Level Full-System Multi-Processor Simulations Using FPGAs,” To appear in ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, February 2008.
•J. Kim, N. Hardavellas, K. Mai, B. Falsafi, J. Hoe, "Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding," ACM/IEEE International Symposium on Microarchitecture, Dec. 2007.
• B. Gold, M. Ferdman, B. Falsaﬁ, K. Mai, “Mitigating Multi-bit Soft Errors in L1 Caches Using Last Store Prediction,” Workshop on Architectural Support for Gigascale Integration, June 2007.
•J. Smolens, B. Gold, J. Hoe, B. Falsaﬁ, K. Mai, “Detecting Emerging Wearout Faults,” Workshop on Silicon Errors in Logic - System Effects April 2007.