Carnegie Mellon University

Seminars

The Department of Electrical and Computer Engineering invites prestigious colleagues to speak during weekly graduate seminars. All talks take place from 12:00 pm–1:00 pm. Please see below for venue details.

 For questions, please contact the committee chair, Tze Meng Low.

View all previously recorded seminars here. Andrew ID and password are required to view recorded seminars.

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Graduate Seminars

All in-person seminars will follow CMU's gathering requirements in place at the time of the seminar. For those seminars taking place virtually, attendees will receive an email before the seminar with login information.

Box lunches/waters will be provided for the in-person seminars at 11:30 am in Panther Hollow Room, CIC 4th floor.

Assistant Professor
Department of Mathematics, Laboratory of Probability, Statistics and Modeling (LPSM)
Sorbonne University, Paris

Title:Federated Learning with Adversarial Nodes

Abstract: The vast amount of data collected every day, combined with the increasing complexity of machine learning models, has led to the emergence of distributed learning schemes. In the now classical Federated learning architecture, the learning procedure consists of multiple data owners (or clients) collaborating to build a global model with the help of a central entity (the server), typically using a distributed variant of SGD. Nevertheless, this algorithm is vulnerable to “misbehaving” clients that could (either intentionally or inadvertently) sabotage the learning by sending arbitrarily bad gradients to the server. These clients are commonly referred to as Byzantine and can model very versatile behaviors going from crashing machines in a datacenter to colluding bots attempting to bias the outcome of a poll on the internet. The purpose of this talk is to present a small introduction to the emerging topic of Byzantine-Robustness. Essentially, the goal is to enhance distributed optimization algorithms, such as distributed SGD, in a way that guarantees convergence despite the presence of some Byzantine clients. We will take the time to present the setting and review some rent results as well as open problems in the community

Bio: Rafael Pinot is an Assistant Professor in the Department of Mathematics at Sorbonne University. He holds a chair in the mathematical foundations of computer and data science within the LPSM research unit, and is a founding member of the Responsible AI initiative at the Sorbonne Center for Artificial Intelligence (SCAI). From 2021 to 2023, he was a postdoctoral researcher at École Polytechnique Fédérale de Lausanne. He completed his Ph.D. in Computer Science at PSL University (Paris Dauphine) and Paris-Saclay University (CEA LIST) from 2017 to 2020. His research centers on statistical machine learning, with a particular focus on the robustness and privacy of learning algorithms.

Alcatel-Lucent Professor of Computer Science
Stanford University

Title: Efficiency in Parallel Runtime Systems

Abstract: What makes a parallel runtime system "efficient"? We present a metric, minimum effective task granularity (METG), that differs in important ways from previous approaches to measuring the performance of runtime systems. We show that METG is generally applicable and can be used to meaningfully compare a wide variety of parallel runtime systems from scientific computing and data analytics. We also present recent results on improving the METG of a class of task-based runtime systems, showing that we are close to reaching the minimum possible METG.

Bio: Alex Aiken is the Alcatel-Lucent Professor of Computer Science at Stanford. Alex received his Bachelor's degree in Computer Science and Music from Bowling Green State University in 1983 and his Ph.D. from Cornell University in 1988. Alex was a Research Staff Member at the IBM Almaden Research Center (1988-1993) and a Professor in the EECS department at UC Berkeley (1993-2003) before joining the Stanford faculty in 2003. His research interests are in areas related to programming languages. He is an ACM Fellow, a recipient of ACM SIGPLAN's Programming Languages Achievement Award and Phi Beta Kappa's Teaching Award, and a former chair of the Stanford Computer Science Department.

Senior Manager of Security Integration and Testing
Rivian

Seminar Location: Singleton Room, Roberts Engineering Hall (12pm)

Title: Shifting Gears on Security: Our Journey with Ethical Hackers

Abstract: While the traditional auto industry sent cease and desist letters to hackers, we sent them invitations. We swapped secrecy for partnership, transforming potential adversaries into essential allies. By working directly with the security research community—welcoming their feedback and collaborating on solutions—we've built a world-class program that makes our vehicles safer for everyone.

Bio: Andrew Kongs works in security and embedded systems, with a focus on automotive cybersecurity. After working for several years in university research, Andrew transitioned to working on security in transportation. He has worked on heavy trucking security research with DARPA, helped improve the security of infotainment and telematics at Toyota, and now manages a cross-functional security team at electric vehicle manufacturer Rivian. His current focus areas are vehicle software security, manufacturing security, and test automation.

Assistant Professor
Carnegie Mellon University

Title: Generative AI for the Cyber-physical World

Abstract: Complex cyber-physical systems are increasingly part of our modern world, in robotics, heavy machinery, medical devices, and beyond. The behavior of these systems is jointly driven by their components, form, and on-board artificial intelligence. As computing and advanced manufacturing techniques expand the types of systems we can build and what built systems around us can do, we require design tools that cut through increasingly complex, often intractable possibilities. Those tools should be accurate, optimizing, explorative, and enable physical realization, to ideate and fabricate machines that approach the diversity and capability of biological life.

In this talk, I will discuss solutions for co-designing dynamical cyber-physical systems, encompassing their physical morphology and embodied artificial intelligence. In particular, I will discuss efficient methods for co-optimizing and co-learning morphology and control, as well as digital fabrication methods that leverage spatially programmable materials for enhanced function, and data-driven modeling for overcoming the simulation-to-real gap. These methods will be tied together in a vision for computational invention.

Bio: Andrew Spielberg is an Assistant Professor in ECE (Robotics Institute and Mechanical Engineering courtesy) at CMU, and CTO of startup company MorphoAI. His mission is to enable anyone to be able to design functional artifacts across scales and domains, and with a special emphasis on rigid and soft robots and other cyber-physical machines. He looks to empower novices and accelerate experts' workflows.

Andrew researches differentiable simulation, design algorithms, digital manufacturing processes, and methods for overcoming the sim-to-real gap, for inventing in both virtual and physical worlds. He has published over 30 papers in top refereed venues, and his work has been recognized with CHI and RA-L best paper awards, ICRA and RoboSoft best paper nominations, Advanced Intelligent Systems journal highlights, and a NeurIPS oral spotlight. He is a recipient of the Unity Global Fellowship, the DARPA I2O Fellowship, and a Harvard GRID $100K award. Andrew received his PhD from MIT's Computer Science and Artificial Intelligence Lab, where he was advised by Daniela Rus and Wojciech Matusik, and has spent time at Harvard University (postdoc), Disney Research Pittsburgh and Zürich, Intel Labs, and Johns Hopkins University Applied Physics Lab.

Assistant Research Professor
USC Department of Computer Science and Research Science
USC Information Sciences Institute

Title: Programming in Persistent Memory: Transactions and Universal Constructions

Abstract: The process of designing and implementing correct concurrent data structures is non-trivial and often error-prone. The recent commercial availability of Non-Volatile Memory (NVM) has prompted many researchers to also consider designing concurrent data structures that persist shared state, allowing the data structure to be recovered following a power failure. These persistent concurrent data structures further complicate the process of achieving correct and efficient implementations.

Much of the existing research regarding persistent concurrent data structures has focused on hand-crafted approaches, which often involve persisting an existing volatile concurrent data structure. Unfortunately, designing efficient and correct hand-crafted persistent data structures is often difficult, time-consuming, and error-prone. Much of the challenge stems from the fact that it is already difficult to achieve correct volatile concurrent data structures.
Alternatively, concurrency can be achieved through the use of transactional memory (TM) and Universal constructions (UCs), which produce a concurrent object given a sequential object.
TMs are synchronization mechanisms that allow users to execute sequences of memory accesses as atomic transactions. Similarly, a persistent TM (PTM) provides the same functionality but also ensures that the effects of transactions are written back to NVM.
Analogously, Persistent universal constructions (PUCs), beyond producing a concurrent object from a sequential object, guarantee that the object can be recovered following a crash.

This talk will present algorithms and complexity bounds for PTMs and PUCs supporting the programmability of persistent concurrent applications. Our results provide insights into the tradeoffs associated with correctness and durability properties, the cost of recovering the application state following a crash, and the actual performance on persistent memory multi-socket CPU architectures.

Bio: Srivatsan Ravi, Ph.D., is Associate Research Professor in USC Dept. of Computer Science and a Research Lead at USC Information Sciences Institute. He also serves as a Senior Scientist at Supra Blockchain Labs. His research interests are centered around the theory and practice of concurrent and distributed computing as well as applications of distributed techniques for networking and privacy-preserving AI/ML computations. He received his bachelor's degree from Anna University (India), his master's degree from Cornell University (New York), and his doctoral degree from the Technical University of Berlin (Germany), where he was a Marie Curie Ph.D Fellow. He has served as PI and Key Personnel on several DARPA and NSF programs, bringing secure distributed techniques to domains like networking and federated learning.

Research Scientist
Bosch Research & Technology Center
Sustainability Research Area Chair, Carnegie Bosch Institute

Title: AI for Cyber-Physical Systems: Identifying the Valuable Gaps

Abstract: AI is rapidly changing the way we interact with and reason about digital data, but making far slower advancements regarding how we interact with the physical world. Using AI to reason about cyber-physical systems helps to close this gap, but simply transferring existing models and techniques into real-time systems will, at best, yield underwhelming results. This talk will define several incompatibilities between current mainstream AI workflows and the requirements of cyber-physical systems, including system interfaces, data availability, and real-time requirements. Using factory automation systems as a recurring example, this talk will explore the feasibility of different approaches and propose several research directions that will affect the long-term usability of AI for real-time, industrial systems.

Bio: Emily Ruppel is a Research Scientist at Bosch Research & Technology Center in Pittsburgh, Pennsylvania, as well as the Sustainability Research Area Chair for the Carnegie-Bosch Institute. Her current research interests lie at the intersection of cyber-physical systems, programming models, and machine learning. Before joining Bosch, she received her Ph.D. in Electrical & Computer Engineering from Carnegie Mellon University, where she studied hardware and software for intermittent computing. Her work has been published in top-tier conferences including MICRO, PLDI, and RTAS.

Research Staff Member
IBM Watson Research Center
Georgia Institute of Technology

Topic: Challenges and Opportunities for Ultra-low Power Design for Quantum Computing Applications

Abstract: This talk will address the practical challenges associated with cryogenic CMOS designs for next-generation quantum computing. Starting from the system level, it will detail the design considerations for a non-multiplexed, semi-autonomous, transmon qubit state controller (QSC) implemented in 14nm CMOS FinFET technology. The QSC includes an augmented general-purpose digital processor that supports waveform generation and phase rotation operations combined with a low-power current-mode single sideband up conversion I/Q mixer-based RF arbitrary waveform generator (AWG). Implemented in 14nm CMOS FinFET technology, the QSC generates control signals in its target 4.5GHz to 5.5 GHz frequency range, achieving an SFDR > 50dB for a signal bandwidth of 500MHz. With the controller operating in the 4K stage of a cryostat and connected to a transmon qubit in the cryostat’s millikelvin stage, measured transmon T1 and T2 coherence times were 75.5μS and 73 μS, respectively, in each case comparable to results achieved using conventional room temperature controls. In further tests with transmons, a qubit-limited error rate of 7.76x10-4 per Clifford gate is achieved, again comparable to results achieved using room temperature controls. The QSC’s maximum RF output power is -18 dBm, and power dissipation per qubit under active control is 23mW. An improved, low-power design version using end-to-end current mode design that achieves half of this power will also be presented.

Bio: Sudipto Chakraborty (B. Tech, IIT, Kharagpur, 1998, Ph.D. from Ga Tech, 2002) was with Texas Instruments till 2016, where he designed low-power ICs for >10 product families in automotive/wireless/medical microcontrollers. Since 2017, he has led the low-power circuit design for next-generation quantum computing applications in IBM research using nanometer CMOS. He has authored or co-authored >85 papers, two books, and 94 US patents. He has served in the TPC, including ISSCC, CICC, RFIC, IMS, and is an IBM master inventor in 2022. He serves as an AE of the (TCAS–I) and distinguished lecturer in the IEEE CASS and SSCS.