Memory Systems Publications

• Memory Controllers
• Emerging Memory Technologies
• Prefetching
• Caching
• Runahead Execution (Latency Tolerance and Memory Level Parallelism)
• Other Memory Level Parallelism
• Speculative Memory References

Memory Controllers

• Yoongu Kim, Dongsu Han, Onur Mutlu, and Mor Harchol-Balter,
  "ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers"
  Proceedings of the 16th International Symposium on High-Performance Computer Architecture (HPCA), Bangalore, India, January 2010.
  
• Onur Mutlu and Thomas Moscibroda,
  "Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Memory Controllers"
  IEEE Micro, Special Issue: Micro's Top Picks from 2008 Computer Architecture Conferences (MICRO TOP PICKS), Vol. 29, No. 1, pages 22-32, January/February 2009.
• Chang Joo Lee, Onur Mutlu, Veynu Narasiman, and Yale N. Patt,
  "Prefetch-Aware DRAM Controllers"
  Proceedings of the 41st International Symposium on Microarchitecture (MICRO), pages 200-209, Lake Como, Italy, November 2008. Slides (ppt)
• Thomas Moscibroda and Onur Mutlu,
  "Distributed Order Scheduling and its Application to Multi-Core DRAM Controllers"
  Proceedings of the 27th Symposium on Principles of Distributed Computing (PODC), pages 365-374, Toronto, ON, Canada, August 2008. Slides (pptx)
  Best Presentation Award.
• Onur Mutlu and Thomas Moscibroda,
  "Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems"
  Proceedings of the 35th International Symposium on Computer Architecture (ISCA), pages 63-74, Beijing, China, June 2008. Slides (ppt)
  One of the 12 computer architecture papers of 2008 selected as Top Picks by IEEE Micro.
• Engin Ipek, Onur Mutlu, José F. Martínez, and Rich Caruana,
  "Self Optimizing Memory Controllers: A Reinforcement Learning Approach"
  Proceedings of the 35th International Symposium on Computer Architecture (ISCA), pages 39-50, Beijing, China, June 2008. Slides (pptx)
• Onur Mutlu and Thomas Moscibroda,
  "Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors"
  Proceedings of the 40th International Symposium on Microarchitecture (MICRO), pages 146-158, Chicago, IL, December 2007. Slides (ppt)
• Thomas Moscibroda and Onur Mutlu,
  "Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems"
  Proceedings of the 16th USENIX Security Symposium (USENIX SECURITY), pages 257-274, Boston, MA, August 2007. Slides (ppt)

Emerging Memory Technologies

• Benjamin C. Lee, Engin Ipek, Onur Mutlu, and Doug Burger,
  "Architecting Phase Change Memory as a Scalable DRAM Alternative"
  Proceedings of the 36th International Symposium on Computer Architecture (ISCA), pages 2-13, Austin, TX, June 2009. Slides (pdf)
  One of the computer architecture papers of 2009 selected as Top Picks by IEEE Micro. Selected as a CACM Research Highlight.

Prefetching

• Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, and Yale N. Patt,
  "Coordinated Control of Multiple Prefetchers in Multi-Core Systems"
  to appear in Proceedings of the 42nd International Symposium on Microarchitecture (MICRO), New York, NY, December 2009.

• Chang Joo Lee, Veynu Narasiman, Onur Mutlu, and Yale N. Patt,
  "Improving Memory Bank-Level Parallelism in the Presence of Prefetching"
  to appear in Proceedings of the 42nd International Symposium on Microarchitecture (MICRO), New York, NY, December 2009.

• Eiman Ebrahimi, Onur Mutlu, and Yale N. Patt,
  "Techniques for Bandwidth-Efficient Prefetching of Linked Data Structures in Hybrid Prefetching Systems"
  Proceedings of the 15th International Symposium on High-Performance Computer Architecture (HPCA), pages 7-17, Raleigh, NC, February 2009. Slides (ppt)
  Best paper session. One of the three papers nominated for the Best Paper Award by the Program Committee.
• Chang Joo Lee, Onur Mutlu, Veynu Narasiman, and Yale N. Patt,
  "Prefetch-Aware DRAM Controllers"
  Proceedings of the 41st International Symposium on Microarchitecture (MICRO), pages 200-209, Lake Como, Italy, November 2008. Slides (ppt)
• Santhosh Srinath, Onur Mutlu, Hyesoon Kim, and Yale N. Patt,
  "Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers"
  Proceedings of the 13th International Symposium on High-Performance Computer Architecture (HPCA), pages 63-74, Phoenix, AZ, February 2007. Slides (ppt)
  One of the five papers nominated for the Best Paper Award by the Program Committee.
• Onur Mutlu, Hyesoon Kim, and Yale N. Patt,
  "Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses"
  IEEE Transactions on Computers (TC), Vol. 55, No. 12, pages 1491-1508, December 2006.
• Onur Mutlu, Hyesoon Kim, and Yale N. Patt,
  "Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns"
  Proceedings of the 38th International Symposium on Microarchitecture (MICRO), pages 233-244, Barcelona, Spain, November 2005. Slides (ppt) Slides (pdf)
  One of the five papers nominated for the Best Paper Award by the Program Committee.
  An extended version as HPS Technical Report, TR-HPS-2006-004, University of Texas at Austin, April 2006.

Caching

• Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, and Yale N. Patt,
  "A Case for MLP-Aware Cache Replacement"
  Proceedings of the 33rd International Symposium on Computer Architecture (ISCA), pages 167-177, Boston, MA, June 2006. Slides (ppt)
• Onur Mutlu, Hyesoon Kim, David N. Armstrong, and Yale N. Patt,
  "Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References"
  International Journal of Parallel Programming (IJPP), Vol. 33, No. 5, pages 529-559, October 2005.
• Onur Mutlu, Hyesoon Kim, David N. Armstrong, and Yale N. Patt,
  "Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance"
  Proceeedings of the 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), pages 2-9, Foz Do Iguacu, PR, Brazil, October 2004. Slides (pdf)

Runahead Execution (Latency Tolerance and Memory Level Parallelism)

• Onur Mutlu, Hyesoon Kim, and Yale N. Patt,
  "Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses"
  IEEE Transactions on Computers (TC), Vol. 55, No. 12, pages 1491-1508, December 2006.
• Onur Mutlu,
  "Efficient Runahead Execution Processors"
  Ph.D. Dissertation, HPS Technical Report, TR-HPS-2006-007, July 2006. Slides (ppt)
  Nominated for the ACM Doctoral Dissertation Award by the University of Texas at Austin.
• Onur Mutlu, Hyesoon Kim, and Yale N. Patt,
  "Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance"
  IEEE Micro, Special Issue: Micro's Top Picks from Microarchitecture Conferences (MICRO TOP PICKS), Vol. 26, No. 1, pages 10-20, January/February 2006. Submitted final version
• Onur Mutlu, Hyesoon Kim, and Yale N. Patt,
  "Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns"
  Proceedings of the 38th International Symposium on Microarchitecture (MICRO), pages 233-244, Barcelona, Spain, November 2005. Slides (ppt) Slides (pdf)
  One of the five papers nominated for the Best Paper Award by the Program Committee.
  An extended version as HPS Technical Report, TR-HPS-2006-004, University of Texas at Austin, April 2006.
• Onur Mutlu, Hyesoon Kim, David N. Armstrong, and Yale N. Patt,
  "An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors"
  IEEE Transactions on Computers (TC), Vol. 54, No. 12, pages 1556-1571, December 2005.
• Onur Mutlu, Hyesoon Kim, and Yale N. Patt,
  "Techniques for Efficient Processing in Runahead Execution Engines"
  Proceedings of the 32nd International Symposium on Computer Architecture (ISCA), pages 370-381, Madison, WI, June 2005. Slides (ppt) Slides (pdf)
  One of the 13 computer architecture papers of 2005 selected as Top Picks by IEEE Micro.
• Onur Mutlu, Hyesoon Kim, David N. Armstrong, and Yale N. Patt,
  "Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References"
  International Journal of Parallel Programming (IJPP), Vol. 33, No. 5, pages 529-559, October 2005.
• Onur Mutlu, Hyesoon Kim, Jared Stark, and Yale N. Patt,
  "On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor"
  IEEE Computer Architecture Letters (CAL), Vol. 4, January 2005.
• Onur Mutlu, Hyesoon Kim, David N. Armstrong, and Yale N. Patt,
  "Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance"
  Proceeedings of the 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), pages 2-9, Foz Do Iguacu, PR, Brazil, October 2004. Slides (pdf)
• Onur Mutlu, Jared Stark, Chris Wilkerson, and Yale N. Patt,
  "Runahead Execution: An Effective Alternative to Large Instruction Windows"
  IEEE Micro, Special Issue: Micro's Top Picks from Microarchitecture Conferences (MICRO TOP PICKS), Vol. 23, No. 6, pages 20-25, November/December 2003.
• Onur Mutlu, Jared Stark, Chris Wilkerson, and Yale N. Patt,
  "Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors"
  Proceedings of the 9th International Symposium on High-Performance Computer Architecture (HPCA), pages 129-140, Anaheim, CA, February 2003. Slides (pdf)
  One of the 15 computer architecture papers of 2003 selected as Top Picks by IEEE Micro.

Other Memory Level Parallelism

• Chang Joo Lee, Veynu Narasiman, Onur Mutlu, and Yale N. Patt,
  "Improving Memory Bank-Level Parallelism in the Presence of Prefetching"
  to appear in Proceedings of the 42nd International Symposium on Microarchitecture (MICRO), New York, NY, December 2009.

• Onur Mutlu and Thomas Moscibroda,
  "Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Memory Controllers"
  IEEE Micro, Special Issue: Micro's Top Picks from 2008 Computer Architecture Conferences (MICRO TOP PICKS), Vol. 29, No. 1, pages 22-32, January/February 2009.
• Onur Mutlu and Thomas Moscibroda,
  "Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems"
  Proceedings of the 35th International Symposium on Computer Architecture (ISCA), pages 63-74, Beijing, China, June 2008. Slides (ppt)
• Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, and Yale N. Patt,
  "A Case for MLP-Aware Cache Replacement"
  Proceedings of the 33rd International Symposium on Computer Architecture (ISCA), pages 167-177, Boston, MA, June 2006. Slides (ppt)

Speculative Memory References

• Chang Joo Lee, Hyesoon Kim, Onur Mutlu, and Yale N. Patt,
  "Performance-Aware Speculation Control using Wrong Path Usefulness Prediction"
  Proceedings of the 14th International Symposium on High-Performance Computer Architecture (HPCA), pages 39-49, Salt Lake City, UT, February 2008. Slides (ppt)
• Onur Mutlu, Hyesoon Kim, David N. Armstrong, and Yale N. Patt,
  "An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors"
  IEEE Transactions on Computers (TC), Vol. 54, No. 12, pages 1556-1571, December 2005.
• Onur Mutlu, Hyesoon Kim, David N. Armstrong, and Yale N. Patt,
  "Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References"
  International Journal of Parallel Programming (IJPP), Vol. 33, No. 5, pages 529-559, October 2005.
• Onur Mutlu, Hyesoon Kim, David N. Armstrong, and Yale N. Patt,
  "Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance"
  Proceeedings of the 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), pages 2-9, Foz Do Iguacu, PR, Brazil, October 2004. Slides (pdf)
• Onur Mutlu, Hyesoon Kim, David N. Armstrong, and Yale N. Patt,
  "Understanding the Effects of Wrong-Path Memory References on Processor Performance"
  Proceedings of the 3rd Workshop on Memory Performance Issues (WMPI), pages 56-64, Munchen, Germany, June 2004. Slides (pdf)
  An extended version as HPS Technical Report, TR-HPS-2005-001, University of Texas at Austin, January 2005.