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project_groups [2009/02/08 20:36] 151.201.54.95 |
project_groups [2010/08/17 18:27] (current) |
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| **Topic:** Prefetching in distributed cache system (NUCA), may extend to multicore (#11)\\ | **Topic:** Prefetching in distributed cache system (NUCA), may extend to multicore (#11)\\ | ||
| \\ | \\ | ||
| - | **Group:** insert group members here\\ | + | **Group:** Kami Vaniea, Akkarit Sangpetch\\ |
| - | **Topic:** insert project topic here\\ | + | **Topic:** Visualizing memory accesses to assist researchers in debugging.\\ |
| + | \\ | ||
| + | **Group:** Jack Cheung, Mark Ma\\ | ||
| + | **Topic:** Fault Tolerance(#5)\\ | ||
| + | \\ | ||
| + | **Group:** Kevin Woo, Yu Cai\\ | ||
| + | **Topic:** Bufferless Routers Implementation (#14)\\ | ||
| + | \\ | ||
| + | **Group:** Adam Hartman, Cindy Tseng\\ | ||
| + | **Topic:** DoS Attacks on On-Chip Interconnect (#4)\\ | ||
| + | \\ | ||
| + | **Group:** Matthew Beckler, Vinod Chandrasekaran\\ | ||
| + | **Topic:** Asymmetric multi-core designs (#6), identifying phases of program operation and scheduling on optimized cores.\\ | ||
| + | \\ | ||
| + | **Group:** Milo Polte, Rob Simmons\\ | ||
| + | **Topic:** Attacking and defending PCM-based main memory, variant of (#19) focusing on PCM as a replacement for DRAM.\\ | ||
| + | \\ | ||
| + | **Group:** Chengjou Liao, Travis Iwanaga\\ | ||
| + | **Topic:** GPU SIMD Thread Scheduling for MLP\\ | ||
| + | \\ | ||
| + | **Group:** Anshul Gandhi, Yi Zhuang\\ | ||
| + | **Topic:** Analytical Modeling of system temperature (inspired by #22).\\ | ||
| + | \\ | ||
| + | **Group:** George Nychis, Tony Cartolano\\ | ||
| + | **Topic:** QoS and Fairness in Bufferless Interconnection On-Chip Networks (#1).\\ | ||
| + | \\ | ||
| + | **Group:** Yanlin Li, Xin Zhang\\ | ||
| + | **Topic:** More is Less: Denial-of-Service Attacks to Multi-Core Systems | ||
| ===== Looking for a project partner? ===== | ===== Looking for a project partner? ===== | ||
| If you are looking for a project partner please post your ad along with your contact information below. If particular topics interest you make sure to mention them.\\ | If you are looking for a project partner please post your ad along with your contact information below. If particular topics interest you make sure to mention them.\\ | ||
| - | \\ | ||
| - | **Name:** Kami Vaniea kami@cs.cmu.edu\\ | ||
| - | **Interests:** Visualizing memory accesses to assist researchers in debugging.\\ | ||
| - | **Ad:** I'd like to build a system to help researchers debug architecture layouts and help them find areas to optimize. I imagine such a system would allow a researcher to view the state of memory at any point in the execution cycle as well as see the series of instructions that lead to the current state for a given memory location. To do this project we would need to build a back tracker which given a sequence of instructions and a memory address could determine which instructions caused the current state of the memory. \\ | ||
| \\ | \\ | ||
| **Name:** Richa Aggawal richaagg@andrew.cmu.edu\\ | **Name:** Richa Aggawal richaagg@andrew.cmu.edu\\ | ||
| **Interests:** I am flexible wid the topics. Anybody looking for a partner, please contact me.\\ | **Interests:** I am flexible wid the topics. Anybody looking for a partner, please contact me.\\ | ||
| \\ | \\ | ||
| + | **Name:** Joon Ho Cho (joonhoch@andrew.cmu.edu)\\ | ||
| + | **Interests:** I wanna work on the Fair/QoS-aware caching in the presence of prefetching (topic #9). Let me know if you want to partner up with me.\\ | ||
| + | \\ | ||
| + | |||
