Post your group members and topics below:
Group: Steve Thompson and Ben Nowak
Topic: Asymmetric Multi-core (#6)

Group: Jialiu Lin, Yi Wu
Topic: Qos Aware (fair) memory controllers in the presence of prefetching (#8)

Group: Yoongu Kim, Dongsu Han
Topic: Preserving bank parallelism in multiple multi-core memory controllers (#2)

Group: Rui Meireles, Sarah Aboutalib
Topic: Feature selection for data prefetchers (#24)

Group: Rashmi Sachdeva, Bob Koutsoyannis
Topic: Prefetching in distributed cache system (NUCA), may extend to multicore (#11)
Group: insert group members here
Topic: insert project topic here

If you are looking for a project partner please post your ad along with your contact information below. If particular topics interest you make sure to mention them.

Name: Kami Vaniea kami@cs.cmu.edu
Interests: Visualizing memory accesses to assist researchers in debugging.
Ad: I'd like to build a system to help researchers debug architecture layouts and help them find areas to optimize. I imagine such a system would allow a researcher to view the state of memory at any point in the execution cycle as well as see the series of instructions that lead to the current state for a given memory location. To do this project we would need to build a back tracker which given a sequence of instructions and a memory address could determine which instructions caused the current state of the memory.

Name: Richa Aggawal richaagg@andrew.cmu.edu
Interests: I am flexible wid the topics. Anybody looking for a partner, please contact me.