Microarchitecture Optimizations for Exploiting MLP

Tuesday February 22, 2005
Hamerschlag Hall D-210
4:00 pm

Eric Chung
Carnegie Mellon University

The performance of memory-bound commercial applications such as databases is limited by increasing memory latencies. Using the epoch model of Memory-Level Parallelism (MLP), Yuan Chou, Brian Fahs, and Santosh Abraham examine in "Microarchitecture Optimizations for Exploiting MLP" how traditional ILP features such as out-of-order issue affect MLP and what implications it has for performance.

In this seminar, I will present their results and unravel how aggressive handling of loads, branches, and serializing instructions is needed to fully benefit from large out-of-order instruction windows. I will also examine how decoupling a processor's issue window and reorder buffer is necessary to exploit MLP more efficiently. Finally, I will discuss the impact of runahead execution and value prediction and future steps for improving MLP.

Eric Chung is a first year PhD student in the Computer Architecture Laboratory at Carnegie Mellon University, where he is advised by Professor James Hoe. He holds a B.S. in Electrical Engineering and Computer Science from the University of California, Berkeley. Eric's research focuses on architectures and fault-tolerant computing.