Eric S. Chung

Computer Architecture Lab (CALCM)
Center for Silicon System Implementation (CSSI)
Department of Electrical & Computer Engineering
Carnegie Mellon University
5000 Forbes Ave.
Hamerschlag Hall, A-314
Pittsburgh, PA 15213

I am a fourth-year Ph.D. candidate advised by Professor James C. Hoe at the Computer Architecture Lab at Carnegie Mellon (CALCM). My research focuses on designing reliable, scalable, and cost-effective server architectures as part of the TRUSS effort.

I am also part of the SimFlex group working on the ProtoFlex project, a hybrid hardware-software FPGA-accelerated emulator developed for practical large-scale shared-memory multiprocessor research. This work is in conjunction with the multi-university RAMP initiative.

I was a teaching assistant for these courses:
Fa'06 Fundamentals of Computer Engineering (18-240 at CMU)
Fa'05 Adv. Computer Architecture (18-741 at CMU)
Sp'04 Comp. & Design Tech. for Dig. Systems (CS150 at UCB)
Fa'03 Intro to Digital Electronics (EE42 at UCB)

I work closely with James C. Hoe, Babak Falsafi, Ken Mai, Brian Gold, Jangwoo Kim, Eriko Nurvitadhi, and Jared Smolens.

I worked previously with my undergraduate research advisor Professor James A. Landay, Professor Jason I. Hong, and Jimmy Lin at the Group for User Interface Research at the University of California Berkeley.

I was also a co-founder of Berkeley Innovation with Menzies Chen, Calliea Pan, and Anthony Yau.

		A Complexity-Effective Architecture for Accelerating Full-System Multiprocessor Simulations Using FPGAs Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, and Ken Mai. International Symposium on Field-Programmable Gate Arrays, February 2008.

		Virtualized Full-System Emulation of Multiprocessors using FPGAs Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai 2nd Workshop on Architectural Research Prototyping in conjunction with the 34th International Symposium on Computer Architecture, San Diego, June 2007.

		ProtoFlex: FPGA-accelerated Hybrid Functional Simulation Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai NSF NGS Workshop at IPDPS, CALCM Technical Report 2007-2, Carnegie Mellon University, February 2007.

		ProtoFlex: FPGA-accelerated Hybrid Functional Simulator Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai January 11, 2007, RAMP 2007 Winter Retreat, Berkeley, CA.

		Combining Simulators and FPGAs: "An Out-of-Body Experience" Eric S. Chung, Brian Gold, James C. Hoe, Babak Falsafi June 22, 2006, RAMP 2006 Summer Retreat, MIT, MA.

		ProtoFlex: Co-Simulation for Component-wise FPGA Emulator Development Eric S. Chung, James C. Hoe, Babak Falsafi Workshop on Architecture Research using FPGA Platforms, 11th International Symposium on High-Performance Computer Architecture, Austin, TX, February 12, 2006

		TRUSS: Reliable, Scalable Server Architecture Brian T. Gold, Jared C. Smolens, Jangwoo Kim, Eric S. Chung, Vasileios Liaskovitis, Eriko Nurvitadhi, Babak Falsafi, James C. Hoe, and Andreas G. Nowatzyk IEEE Micro, Special Issue on Reliability-Aware Microarchitectures, November-December 2005.

		Opportunity of Hardware-based Optimistic Concurrency in OLTP Jangwoo Kim, Eriko Nurvitadhi, Eric S. Chung Selected Project Reports from Advanced OS & Distributed Systems, Spring 2005. Technical report CMU-CS-05-138.

		Design Patterns for Ubiquitous Computing Eric Chung, Jason I. Hong, James Lin, Madhu K. Prabaker, James A. Landay, and Alan L. Liu Proceedings of Designing Interactive Systems 2004. Cambridge, Massachusetts. August, 2004.

		Design Patterns for Ubiquitous Computing. Presentation at the Berkeley Intel Research Center, Berkeley, CA. August, 2003.

		Design and Comparison of 64-bit Re-configurable Adders. Advanced Digital Integrated Circuits course project supervised by Borijove Nikolic. Berkeley, CA. July 2004.