Fifteenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2010)
Sheraton Station Square
Pittsburgh, PA - March 13~17, 2010
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====== Technical Program ====== | ====== Technical Program ====== | ||
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+ | The [[http://llvm.cs.uiuc.edu/~vadve/asplos10-pcchair-report.pdf | Program Chair's Report]] is now available. | ||
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===== Saturday, March 13, 2010 ===== | ===== Saturday, March 13, 2010 ===== | ||
- | ** Full Day ** | + | ** Full-Day Events** (refer to individual event pages for start and finish time) |
* [[http://sysrun.haifa.il.ibm.com/hrl/wiov2010/ | Workshop on I/O Virtualization (WIOV)]], //Scott Rixner (rixner@rice.edu)// | * [[http://sysrun.haifa.il.ibm.com/hrl/wiov2010/ | Workshop on I/O Virtualization (WIOV)]], //Scott Rixner (rixner@rice.edu)// | ||
* [[http://www.engr.pitt.edu/electrical/faculty-staff/akjones/INTERACT/ | Workshop on Interaction Between Compilers and Computer Architectures (INTERACT)]], //Alex Jones (akjones@ece.pitt.edu)// | * [[http://www.engr.pitt.edu/electrical/faculty-staff/akjones/INTERACT/ | Workshop on Interaction Between Compilers and Computer Architectures (INTERACT)]], //Alex Jones (akjones@ece.pitt.edu)// | ||
- | * [[PM-T_blurb | Tutorial on Performance Monitoring using Hardware Performance Events ]], //Ramesh Peri (Ramesh.v.peri@intel.com)// | + | * <del>[[PM-T_blurb | Tutorial on Performance Monitoring using Hardware Performance Events ]], //Ramesh Peri (Ramesh.v.peri@intel.com)//</del> (cancelled) |
- | **10:00- 10:30.** | + | **8:00-9:00. Breakfast** |
- | * Morning break (light refreshments) | + | |
- | **3:00- 3:30.** | + | **10:00- 10:45. Morning break** |
- | *Afternoon break (light refreshments) | + | |
+ | **12:00- 1:45. Lunch (for Full Day Saturday attendees)** | ||
+ | |||
+ | **3:00- 3:45. Afternoon break** | ||
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===== Sunday, March 14, 2010 ===== | ===== Sunday, March 14, 2010 ===== | ||
- | ** Full Day ** | + | **Daylight Saving Time starts today!!** |
+ | |||
+ | ** Full-Day Events ** (refer to individual event pages for start and finish time) | ||
* [[http://www.ece.neu.edu/groups/nucar/GPGPU/ | Workshop on General-Purpose Computation on Graphics Processing Units (GPGPU)]], //David Kaeli (kaeli@ece.neu.edu)// | * [[http://www.ece.neu.edu/groups/nucar/GPGPU/ | Workshop on General-Purpose Computation on Graphics Processing Units (GPGPU)]], //David Kaeli (kaeli@ece.neu.edu)// | ||
- | ** Morning ** | + | ** Morning Events** (refer to individual event pages for start and finish time) |
* [[http://www.cs.virginia.edu/~skadron/rodinia_asplos10.html | Tutorial on the Rodinia Benchmark Suite for Heterogeneous Computing]], //Kevin Skadron (skadron@cs.virginia.edu)// | * [[http://www.cs.virginia.edu/~skadron/rodinia_asplos10.html | Tutorial on the Rodinia Benchmark Suite for Heterogeneous Computing]], //Kevin Skadron (skadron@cs.virginia.edu)// | ||
* [[http://www.cse.psu.edu/~yuanxie/ASPLOS10-tutorial.html | Tutorial on Emerging Technologies and Their Impact on System Design]], //Norm Jouppi (Norm.Jouppi@hp.com)// | * [[http://www.cse.psu.edu/~yuanxie/ASPLOS10-tutorial.html | Tutorial on Emerging Technologies and Their Impact on System Design]], //Norm Jouppi (Norm.Jouppi@hp.com)// | ||
- | ** Afternoon ** | + | ** Afternoon Events** (refer to individual event pages for start and finish time) |
* [[http://www.eecs.umich.edu/exert/ | Exascale Evaluation and Research Techniques Workshop (EXERT)]], //Tom Wenisch (twenisch@umich.edu)// | * [[http://www.eecs.umich.edu/exert/ | Exascale Evaluation and Research Techniques Workshop (EXERT)]], //Tom Wenisch (twenisch@umich.edu)// | ||
* [[WAMT_blurb | Workshop on Architecting Memory Technologies (WAMT)]], //Shih-Lien Lu (shih-lien.l.lu@intel.com)// | * [[WAMT_blurb | Workshop on Architecting Memory Technologies (WAMT)]], //Shih-Lien Lu (shih-lien.l.lu@intel.com)// | ||
- | **10:00- 10:30.** | + | **8:00-9:00. Breakfast** |
- | * Morning break (light refreshments) | + | |
- | **3:00- 3:30.** | + | **10:00- 10:45. Morning break** |
- | * Afternoon break (light refreshments) | + | |
- | **6:30- 9:30.** | + | **12:00- 1:45. Lunch (for Full Day Sunday attendees)** |
- | * Opening Reception and [[acceptedposters | Poster Session]], Conference Hotel | + | |
+ | **3:00- 3:45. Afternoon break** | ||
+ | |||
+ | **6:30- 9:30. Opening Reception and [[acceptedposters | Poster Session]], Conference Hotel** (supported by VMware) | ||
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**8:45- 9:00. Chairs' Welcome** | **8:45- 9:00. Chairs' Welcome** | ||
- | **9:00- 9:50. Session 1: Novel Architectures** | + | **9:00- 9:50. Session 1: Novel Architectures (Session Chair: Luis Ceze)** |
* Dynamically Replicated Memory: Building Reliable Systems from Nanoscale Resistive Memories, //Engin Ipek, Jeremy Condit, Edmund B. Nightingale, Doug Burger and Thomas Moscibroda (University of Rochester / Microsoft Research)// | * Dynamically Replicated Memory: Building Reliable Systems from Nanoscale Resistive Memories, //Engin Ipek, Jeremy Condit, Edmund B. Nightingale, Doug Burger and Thomas Moscibroda (University of Rochester / Microsoft Research)// | ||
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* A Power-efficient All-optical On-chip Interconnect Using Wavelength-based Oblivious Routing, //Nevin Kirman and Jose Martinez (Cornell University)// | * A Power-efficient All-optical On-chip Interconnect Using Wavelength-based Oblivious Routing, //Nevin Kirman and Jose Martinez (Cornell University)// | ||
- | **9:50-10:40. Session 2: Compilers and Runtime Systems** | + | **9:50-10:40. Session 2: Compilers and Runtime Systems (Session Chair: Michael Hind)** |
* A Real System Evaluation of Hardware Atomicity for Software Speculation, //Naveen Neelakantam, David Ditzel and Craig Zilles (University of Illinois at Urbana-Champaign; Intel)// | * A Real System Evaluation of Hardware Atomicity for Software Speculation, //Naveen Neelakantam, David Ditzel and Craig Zilles (University of Illinois at Urbana-Champaign; Intel)// | ||
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* Technology for Developing Regions: Moore's Law is Not Enough, //Eric Brewer (University of California, Berkeley)// | * Technology for Developing Regions: Moore's Law is Not Enough, //Eric Brewer (University of California, Berkeley)// | ||
- | **12:10-1:40. Lunch.** | + | **12:10-1:40. Lunch.** (supported in part by AMD and by IBM Research) |
- | **1:40-2:55. Session 3: Parallel Programming 1** | + | **1:40-2:55. Session 3: Parallel Programming 1 (Session Chair: Yuanyuan Zhou)** |
- | * CoreDet: A Compiler and Runtime System for Deterministic Multithreaded Execution, //Tom Bergan, Owen Anderson, Joe Devietti, Luis Ceze and Dan Grossman, (University of Washington)// | + | * CoreDet: A Compiler and Runtime System for Deterministic Multithreaded Execution, //Tom Bergan, Owen Anderson, Joe Devietti, Luis Ceze and Dan Grossman (University of Washington)// |
- | * Speculative Parallelization Using Software Multi-threaded Transactions, //Arun Raman, Hanjun Kim, Thomas R. Mason, Thomas B. Jablin and David I. August, (Princeton University)// | + | * Speculative Parallelization Using Software Multi-threaded Transactions, //Arun Raman, Hanjun Kim, Thomas R. Mason, Thomas B. Jablin and David I. August (Princeton University)// |
* Respec: Efficient online multiprocessor replay via speculation and external determinism, //Dongyoon Lee, Benjamin Wester, Kaushik Veeraraghavan, Satish Narayanasamy, Peter Chen and Jason Flinn (University of Michigan)// | * Respec: Efficient online multiprocessor replay via speculation and external determinism, //Dongyoon Lee, Benjamin Wester, Kaushik Veeraraghavan, Satish Narayanasamy, Peter Chen and Jason Flinn (University of Michigan)// | ||
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**2:55-3:25. Afternoon Break** | **2:55-3:25. Afternoon Break** | ||
- | **3:25-5:05. Session 4: Scheduling in Parallel Systems** | + | **3:25-5:05. Session 4: Scheduling in Parallel Systems (Session Chair: Tim Harris)** |
- | * Probabilistic Job Symbiosis Modeling for SMT Processor Scheduling, //Stijn Eyerman and Lieven Eeckhout, (Ghent University)// | + | * Probabilistic Job Symbiosis Modeling for SMT Processor Scheduling, //Stijn Eyerman and Lieven Eeckhout (Ghent University)// |
- | * Request Behavior Variations, // Kai Shen, (University of Rochester)// | + | * Request Behavior Variations, // Kai Shen (University of Rochester)// |
- | * Decoupling contention management from scheduling, // Ryan Johnson, Radu Stoica, Anastasia Ailamaki and Todd Mowry, (Ecole Polytechnique Federale de Lausanne; Carnegie Mellon University)// | + | * Decoupling contention management from scheduling, // Ryan Johnson, Radu Stoica, Anastasia Ailamaki and Todd Mowry (EPFL; Carnegie Mellon University)// |
- | * Addressing Shared Resource Contention in Multicore Processors Via Scheduling, // Sergey Zhuravlev, Sergey Blagodurov and Alexandra Fedorova, (Simon Fraser University)// | + | * Addressing Shared Resource Contention in Multicore Processors Via Scheduling, // Sergey Zhuravlev, Sergey Blagodurov and Alexandra Fedorova (Simon Fraser University)// |
- | **5:30-7:00. Wild and Crazy Ideas (WACI). //Session Chair: Seth Copen Goldstein. (Carnegie Mellon University)//** | + | **5:30-7:00. Wild and Crazy Ideas (WACI). //Session Chair: Seth Copen Goldstein. (Carnegie Mellon University)//** (supported by Google) |
* Short presentations of your best and WACIest ideas. | * Short presentations of your best and WACIest ideas. | ||
- | **7:00- 9:30.** | + | **7:30- 9:30. Reception, Carnegie Mellon University.** (supported by Google) Multiple chartered [[http://www.mollystrolleys.com/PGH_Home.html| Molly's Trolleys]] will make round trips between CMU and Sheraton continuously between 7pm and 10:30pm. |
- | * Outing and Reception, Carnegie Mellon University. (Multiple chartered trolleys will make round trips between CMU and Sheraton continuously between 6:45pm and 10:00pm.) | + | |
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===== Tuesday, March 16, 2010 ===== | ===== Tuesday, March 16, 2010 ===== | ||
- | **9am-10:40am Session 5. Software Reliability** | + | **9am-10:40am Session 5. Software Reliability (Session Chair: Emery Berger)** |
* SherLog: Error Diagnosis by Connecting Clues from Run-time Logs, // Ding Yuan, Haohui Mai, Weiwei Xiong, Lin Tan, Yuanyuan Zhou and Shankar Pasupathy (University of California, San Diego; University of Illinois at Urbana-Champaign) // | * SherLog: Error Diagnosis by Connecting Clues from Run-time Logs, // Ding Yuan, Haohui Mai, Weiwei Xiong, Lin Tan, Yuanyuan Zhou and Shankar Pasupathy (University of California, San Diego; University of Illinois at Urbana-Champaign) // | ||
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**10:40-11:10 Morning Break** | **10:40-11:10 Morning Break** | ||
- | **11:10-12:25. Session 6. Hardware Power and Energy** | + | **11:10-12:25. Session 6. Hardware Power and Energy (Session Chair: David Wood)** |
* Characterizing Processor Thermal Behavior, // Francisco J. Mesa-Martínez, Ehsan K. Ardestani and Jose Renau (University of California, Santa Cruz)// | * Characterizing Processor Thermal Behavior, // Francisco J. Mesa-Martínez, Ehsan K. Ardestani and Jose Renau (University of California, Santa Cruz)// | ||
- | * Conservation Cores: Reducing the Energy of Mature Computations, // Ganesh Venkatesh, John Sampson, Nathan Goulding, Saturnino Garcia, Vladyslav Bryksin, Jose Lugo-Martinez, Steve Swanson and Michael Taylor, (University of California, San Diego)// | + | * Conservation Cores: Reducing the Energy of Mature Computations, // Ganesh Venkatesh, John Sampson, Nathan Goulding, Saturnino Garcia, Vladyslav Bryksin, Jose Lugo-Martinez, Steve Swanson and Michael Taylor (University of California, San Diego)// |
- | * Micro-Pages: Increasing DRAM Efficiency with Locality-Aware Data Placement, // Kshitij Sudan, Niladrish Chatterjee, David Nellans, Manu Awasthi, Rajeev Balasubramonian and Al Davis, (University of Utah)// | + | * Micro-Pages: Increasing DRAM Efficiency with Locality-Aware Data Placement, // Kshitij Sudan, Niladrish Chatterjee, David Nellans, Manu Awasthi, Rajeev Balasubramonian and Al Davis (University of Utah)// |
- | **12:25-1:55 Lunch.** | + | **12:25-1:55 Lunch.** (supported in part by Microsoft and by SUN) |
- | **1:55-2:45. Session 7. Data Centers** | + | **1:55-2:45. Session 7. Data Centers (Session Chair: Scott Mahlke)** |
- | * Power Routing: Dynamic Power Provisioning in the Data Center, // Steven Pelley, David Meisner, Pooya Zandevakili, Jack Underwood and Thomas Wenisch, (University of Michigan)// | + | * Power Routing: Dynamic Power Provisioning in the Data Center, // Steven Pelley, David Meisner, Pooya Zandevakili, Jack Underwood and Thomas Wenisch (University of Michigan)// |
- | * Joint Optimization of Idle and Cooling Power in Data Centers While Maintaining Response Time, // Faraz Ahmad and T. N. Vijaykumar (Purdue University) // | + | * Joint Optimization of Idle and Cooling Power in Data Centers While Maintaining Response Time // Faraz Ahmad and T. N. Vijaykumar (Purdue University) // |
- | **2:45-3:35. Session 8. Hardware Monitoring** | + | **2:45-3:35. Session 8. Hardware Monitoring (Session Chair: Peter Chen)** |
- | * Butterfly Analysis: Adapting Dataflow Analysis to Dynamic Parallel Monitoring, // Michelle Goodstein, Evangelos Vlachos, Shimin Chen, Phillip Gibbons, Michael Kozuch and Todd Mowry, (Carnegie Mellon University)// | + | * Butterfly Analysis: Adapting Dataflow Analysis to Dynamic Parallel Monitoring, // Michelle Goodstein, Evangelos Vlachos, Shimin Chen, Phillip Gibbons, Michael Kozuch and Todd Mowry (Carnegie Mellon University; Intel Labs Pittsburgh)// |
- | * ParaLog: Enabling and Accelerating Online Parallel Monitoring of Multithreaded Applications, // Evangelos Vlachos, Michelle Goodstein, Michael Kozuch, Shimin Chen, Babak Falsafi, Phillip Gibbons and Todd Mowry, (Ecole Polytechnique Federale de Lausanne; Carnegie Mellon University)// | + | * ParaLog: Enabling and Accelerating Online Parallel Monitoring of Multithreaded Applications, // Evangelos Vlachos, Michelle Goodstein, Michael Kozuch, Shimin Chen, Babak Falsafi, Phillip Gibbons and Todd Mowry (Carnegie Mellon University; Intel Labs Pittsburgh; EPFL)// |
**3:35-4:05. Break.** | **3:35-4:05. Break.** | ||
- | **4:05-5:20. Session 9. Parallel Programming 2** | + | **4:05-5:20. Session 9. Parallel Programming 2 (Session Chair: Tim Harris)** |
* MacroSS: Macro-SIMDization of Streaming Applications, // Amir Hormati, Yoonseo Choi, Mark Woh, Manjunath Kudlur, Rodric Rabbah, Trevor Mudge and Scott Mahlke (University of Michigan) // | * MacroSS: Macro-SIMDization of Streaming Applications, // Amir Hormati, Yoonseo Choi, Mark Woh, Manjunath Kudlur, Rodric Rabbah, Trevor Mudge and Scott Mahlke (University of Michigan) // | ||
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* COMPASS: A Programmable Data Prefetcher Using Idle GPU Shaders, // Dong Hyuk Woo and Hsien-Hsin Lee (Georgia Institute of Technology) // | * COMPASS: A Programmable Data Prefetcher Using Idle GPU Shaders, // Dong Hyuk Woo and Hsien-Hsin Lee (Georgia Institute of Technology) // | ||
- | * Flexible Architectural Support for Fine-grain Scheduling, // Daniel Sanchez, Richard Yoo and Christos Kozyrakis, (Stanford University) // | + | * Flexible Architectural Support for Fine-grain Scheduling, // Daniel Sanchez, Richard Yoo and Christos Kozyrakis (Stanford University) // |
- | ** Evening (Time TBA). ** | + | **6:00-9:30. Banquet, Heinz History Center.** (supported in part by HP and by Intel) Multiple chartered [[http://www.mollystrolleys.com/PGH_Home.html| Molly's Trolleys]] will make round trips between the Heinz Center and Sheraton continuously between 5:45pm and 10:15pm. |
- | * Outing and Banquet, Heinz History Center. (Transportation Provided) | + | |
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===== Wednesday, March 17, 2010 ===== | ===== Wednesday, March 17, 2010 ===== | ||
- | **9am-10:40am Session 10. Parallel Memory Systems** | + | **9am-10:40am Session 10. Parallel Memory Systems (Session Chair: Carl Waldspurger)** |
- | * Specifying and Dynamically Verifying Address Translation-Aware Memory Consistency, // Bogdan Romanescu, Alvin Lebeck and Daniel Sorin, (Duke University)// | + | * Specifying and Dynamically Verifying Address Translation-Aware Memory Consistency, // Bogdan Romanescu, Alvin Lebeck and Daniel Sorin (Duke University)// |
- | * Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems, // Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu and Yale Patt, (The University of Texas at Austin)// | + | * Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems, // Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu and Yale Patt (The University of Texas at Austin; Carnegie Mellon University)// |
* An Asymmetric Distributed Shared Memory Model for Heterogeneous Parallel Systems, // Isaac Gelado, Javier Cabezas, John Stone, Sanjay Patel, Nacho Navarro and Wen-mei Hwu (University of Illinois at Urbana- Champaign; UPC)// | * An Asymmetric Distributed Shared Memory Model for Heterogeneous Parallel Systems, // Isaac Gelado, Javier Cabezas, John Stone, Sanjay Patel, Nacho Navarro and Wen-mei Hwu (University of Illinois at Urbana- Champaign; UPC)// | ||
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**10:40-11:10 Break.** | **10:40-11:10 Break.** | ||
- | **11:10-12:25. Session 11. Security and Hardware Reliability** | + | **11:10-12:25. Session 11. Security and Hardware Reliability (Session Chair: Vikram Adve)** |
* Orthrus: Efficient Software Integrity Protection on Multi-Cores, // Ruirui Huang, Dan Deng and G. Edward Suh (Cornell University)// | * Orthrus: Efficient Software Integrity Protection on Multi-Cores, // Ruirui Huang, Dan Deng and G. Edward Suh (Cornell University)// | ||
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* Shoestring: Probabilistic Soft-error Resilience on the Cheap, // Shuguang Feng, Shantanu Gupta, Amin Ansari and Scott Mahlke (University of Michigan)// | * Shoestring: Probabilistic Soft-error Resilience on the Cheap, // Shuguang Feng, Shantanu Gupta, Amin Ansari and Scott Mahlke (University of Michigan)// | ||
- | * Virtualized and Flexible ECC for Main Memory, // Doe Hyun Yoon and Mattan Erez, (The university of Texas at Austin)// | + | * Virtualized and Flexible ECC for Main Memory, // Doe Hyun Yoon and Mattan Erez (The university of Texas at Austin)// |
+ | x |