GraphGen-based Convolutional Neural Network for the ZedBoard

This page hosts a Convolutional Neural Network demo for the ZedBoard built using the GraphGen compiler.

The GraphGen compiler generates complete, optimized FPGA implementations of graph computations from a high level specification. The paper (linked above) describes the operation of the GraphGen compiler in detail.

In order to use the GraphGen compiler, the application developer provides:

1. A description of the structure of the graph, including the types of data stored at each vertex and edge;
2. An update function to apply to vertices of the graph to perform the computation. This function consists of calls to accelerator functions that are applied to the vertex, it's neighbors, and the edges connecting it to its neighbors;
3. An RTL implementation of the accelerator functions used by the update function. This implementation may be generated by a C-to-gates tool

As illustrated in the image above, the GraphGen compiler partitions the graph into sub-graphs that will fit into the limited on-chip storage space of the FPGA, and generates an application that executes the graph application by fetching each sub-graph from DRAM and performing the update function on each of its vertices. The memory image header produced by the GraphGen compiler is combined with actual graph data for any instance of the computation, allowing the application to be used with any problem instance matching the graph description. Applications generated by the GraphGen compiler use the CoRAM FPGA memory abstraction to interact with DRAM and transfer data between the host computer and FPGA board.

This neural network demo is a handwriting recognition application that uses a http://www.codeproject.com/Articles/16650/publicly available neural network that recognizes handwritten digits from the MNIST data set. In our 2014 FCCM paper referenced above, we show results of accelerating this neural network on the Xilinx ML605 FPGA and Terasic DE4 FPGA using an Altera chip. This demo demonstrates the neural network on the ZedBoard, an inexpensive board that includes the Xilinx Zynq 7020 FPGA, a System-on-Chip that also includes two ARM cores. The demo uses software running on an ARM core to support host communications through the ZedBoard's ethernet interface, and communicate with the GraphGen-created processing system through an AXI slave interface. The processing system connects to the ZedBoard's DRAM through the Zynq chip's high performance AXI ports.