CoRAM Online Demo - now supporting both the ML605 and DE4

This page hosts a limited-feature compiler that demonstrates the emulation of CoRAM on conventional FPGAs. The end-user develops an application using: 1) a high-level control thread specification and 2) application core logic developed in HDL (e.g., Verilog). Corflow automatically transforms the input into a stand-alone working design for a given target FPGA platform. The 40-minute video below gives a tutorial that walks the user through a simple design example (Matrix-Vector Multiplication) followed by incremental optimization steps.

Step 1: Watch Tutorial

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Step 2: Select Hardware Options

Network-on-Chip
User Clock
Platform
Useful definition files
Step 3: Enter Control Thread Program Description

Or select an existing design:


Step 4: Enter Core Logic in Verilog



Step 5: Generate Design

The generated Verilog files and scripts from this website are for internal, non-commercial, academic research use only and is not for redistribution, with or without modifications. You may not use the name "Carnegie Mellon University" or derivations thereof to endorse or promote products derived from this software.

THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT, SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY, CONTRACT, TORT OR OTHERWISE).


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corflow_beta.txt · Last modified: 2012/11/30 08:59 by gweisz
 
 
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