This page hosts a limited-feature compiler that demonstrates the emulation of CoRAM on conventional FPGAs. The end-user develops an application using: 1) a high-level control thread specification and 2) application core logic developed in HDL (e.g., Verilog). Corflow automatically transforms the input into a stand-alone working design for a given target FPGA platform. The 40-minute video below gives a tutorial that walks the user through a simple design example (Matrix-Vector Multiplication) followed by incremental optimization steps.
The demo on this page supports the Xilinx ML605 and Terasic (Altera) DE4. If you would like to use CoRAM with the Zynq please send Gabe a message.
Step 1: Watch Tutorial
Download Powerpoint Slides
Step 2: Select Hardware Options