Three files are required to build a system with CoRAM:

1. The compute component source code file, commonly Verilog, that describes the hardware performing computation
2. The control thread source code, written in C, that coordinates data transfers and synchronization
3. The system specification file, a configuration file that describes how the system will be built, and is often standard to the output platform

In addition to these files, there may also be a memory image file containing input data.

This file contains HDL descriptions of the hardware components that implement computation. It is generally written in Verilog, but can also be written in Bluespec System Verilog (if the Bluespec compiler is available) and compiled to Verilog.

It looks like any other Verilog file, with the addition of CoRAM specific components that it instantiates. The three CoRAM specific components are CoRAM modules, Channel FIFO modules, and Channel Registers.

1. CoRAM modules are memories that interact with the hardware components as single ported block memories with a 1 cycle delay on read. These modules are used to hold data brought from or sent to DRAM (or communicated off chip)
2. Channel FIFO modules provide two way queues for communication with control threads. Each queue is 64 entries deep and 64 bits wide.
3. Channel Registers provide a single register that can be used to communicate with control threads. Each register is 64 bits wide.

The compute components may link to other modules defined in external tools. These modules can be any modules supported by the toolset used for simulation and synthesis, and may even be created by high level synthesis tools such as ROCCC, Xilinx Vivado High Level Synthesis, or Altera C2H, and linking the block memory connections from the cores created by these tools to CoRAM modules.

Detailed CoRAM Hardware Instantiation