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coram_files [2012/11/29 19:31] gweisz |
coram_files [2012/11/29 19:32] gweisz |
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| - ports_per_mc - Network ports connected to the memory controller. Must be 4 to reach maximum bandwidth, but may be reduced to create smaller designs. | - ports_per_mc - Network ports connected to the memory controller. Must be 4 to reach maximum bandwidth, but may be reduced to create smaller designs. | ||
| - dram_delay_cycles - Fixed DRAM delay for simulations | - dram_delay_cycles - Fixed DRAM delay for simulations | ||
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