This shows you the differences between two versions of the page.
Both sides previous revision Previous revision | Next revision Both sides next revision | ||
coram_files [2012/11/29 18:57] gweisz |
coram_files [2012/11/29 19:31] gweisz |
||
---|---|---|---|
Line 41: | Line 41: | ||
[[Detailed CoRAM Control Thread]] | [[Detailed CoRAM Control Thread]] | ||
+ | ==== System Specification File ==== | ||
+ | The system specification file can be used for advanced tuning, to provide more control over how the system is built. In general, it does not have to be modified, as a default file for each supported platform is often sufficient. Important parameters are: | ||
+ | - platform - Determines general built type. Use "ml605" for hardware (either the Xilinx ML605 or Terasic/Altera DE4), "ml605sim" for simulation with icarus, or "vsim" for simulation with isim. Simulation targets model dram accesses as having a fixed delay (specified in cycles) | ||
+ | - num_mc - Determines the number of memory controllers (and caches) to use. This should be 1 for the ML605, can be 1 or 2 for the DE4, and can be any number for simulation | ||
+ | - topology - Network topology to use. Can be "xbar" for a crossbar, or "ring" for a unidirectional ring | ||
+ | - ports_per_mc - Network ports connected to the memory controller. Must be 4 to reach maximum bandwidth, but may be reduced to create smaller designs. | ||
+ | - dram_delay_cycles - Fixed DRAM delay for simulations | ||
+ | - | ||