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- | ===== ===== | + | ====== ====== |
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+ | <font size=5><b>Overview</b></font> | ||
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- | In the quest for energy-efficient computing, Field Programmable Gate Arrays (FPGAs) have emerged as a class of general-purpose accelerators with high potential to address the increasing demand for performance while reducing energy consumption. Despite their raw capabilities, today's commodity FPGAs are impractical as general-purpose computing devices. When developing an application for an FPGA, designers are often confronted by: (1) low-level, error-prone hardware description languages (HDL), (2) ``bare-bones'' fabric with nothing but a sea of logic and I/O pins, and (3) low-level, vendor-specific interfaces and gateware that the application must be made compatible with. | + | In the quest for energy-efficient computing, [[http://en.wikipedia.org/wiki/Field-programmable_gate_array|Field Programmable Gate Arrays (FPGAs)]] have emerged as a class of general-purpose accelerators with significant potential for addressing the increasing demands for performance while reducing energy consumption simultaneously. Despite their raw capabilities, today's commodity FPGAs are impractical as general-purpose computing devices. When developing an application for an FPGA, designers are often confronted by: (1) low-level, error-prone hardware description languages (HDL), (2) ``bare-bones'' fabric with nothing but a sea of logic and I/O pins, and (3) low-level, vendor-specific interfaces and gateware that the application must be made compatible with. |
- | {{ coram-top.png?400 |}} | + | {{ coram-top.png?400|}} |
- | To address these limitations, the **Connected RAM (CoRAM) memory architecture** is an endeavor to standardize and simplify how FPGA computing applications interact with memory and I/O, which is a critical step towards a portable FPGA abstraction. CoRAM presents a programmable, customizable view of memory that can be retargeted to different devices and platforms (see Figure above). The abstraction modifies the traditional FPGA's on-die SRAMs to act as in-fabric distributed portals to off-chip memory and I/O. A salient feature of CoRAM is the ability to program these customizable, on-die SRAMs using a software control thread that is portable and easy-to-use (see Figure, right). Compared to the traditional approach where the FPGA memory hierarchy and I/O sub-system is hand-built at the RTL-level for each application, the CoRAM memory architecture can be used to efficiently support a broad range of applications. | + | To address these limitations, the **Connected RAM (CoRAM) memory architecture** is an endeavor to standardize and simplify how FPGA computing applications interact with memory and I/O, which is a critical step towards a portable FPGA abstraction. CoRAM presents a programmable, customizable view of memory that can be retargeted to different devices and platforms (see Figure, right). The abstraction modifies the traditional FPGA's on-die SRAMs to act as in-fabric distributed portals to off-chip memory and I/O. A salient feature of CoRAM is the ability to program these customizable, on-die SRAMs using a software control thread that is portable and easy-to-use. Compared to the traditional approach where the FPGA memory hierarchy and I/O sub-system is hand-built at the RTL-level for each application, the CoRAM memory architecture can be used to efficiently support a broad range of applications. |
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+ | \\ | ||
+ | {{ http://www.youtube.com/v/fbzniv5nuNg?.swf?400x333 }} | ||
===== People ===== | ===== People ===== | ||
**Faculty:** [[http://www.ece.cmu.edu/~jhoe|James C. Hoe]], [[http://www.ece.cmu.edu/directory/details/298/|Ken Mai]]\\ | **Faculty:** [[http://www.ece.cmu.edu/~jhoe|James C. Hoe]], [[http://www.ece.cmu.edu/directory/details/298/|Ken Mai]]\\ | ||
- | **Students:** [[http://www.ece.cmu.edu/~echung|Eric S. Chung]], [[http://www.cs.cmu.edu/~mpapamic|Michael K. Papamichael]], [[http://www.cs.cmu.edu/~gweisz|Gabriel Weisz]], Cagla Cakir, Yu Wang | + | **Students:** [[http://www.ece.cmu.edu/~echung|Eric S. Chung]], [[http://www.cs.cmu.edu/~mpapamic|Michael K. Papamichael]], [[http://www.cs.cmu.edu/~gweisz|Gabriel Weisz]], Cagla Cakir, Yu Wang, Marie Nguyen, Joseph Melber |
===== Acknowledgments ===== | ===== Acknowledgments ===== | ||
- | This work is funded by the National Science Foundation (CCF-1012851). | + | Funding for this work is provided, in part, by the National Science Foundation (CCF-1012851) and by Altera. We thank Altera and Xilinx for their donation of tools and hardware. |
===== Related ===== | ===== Related ===== | ||
- | **{{http://www.ece.cmu.edu/calcm/carl2010|Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL 2010)}}** | + | **[[graphgencnn|Convolutional Neural Network Demo using the GraphGen compiler and CoRAM back end]]** |
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+ | **{{http://www.ece.cmu.edu/calcm/carl|Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL 2013)}}** | ||
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+ | **{{https://github.com/shtaxxx/PyCoRAM|PyCoRAM - A Python-based Implementation of the CoRAM Memory Architecture.}}** | ||
+ | |||
+ | **{{http://www.ece.cmu.edu/~calcm/carl/doku.php?id=wiki:carl2012|Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL 2012)}}** | ||
+ | |||
+ | **{{http://www.ece.cmu.edu/~calcm/carl/doku.php?id=wiki:carl2010|Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL 2010)}}** | ||
===== Affiliations ===== | ===== Affiliations ===== | ||
**{{http://www.ece.cmu.edu/~calcm|Computer Architecture Lab at Carnegie Mellon}}**\\ | **{{http://www.ece.cmu.edu/~calcm|Computer Architecture Lab at Carnegie Mellon}}**\\ | ||
**{{http://www.nsf.gov|National Science Foundation}}** | **{{http://www.nsf.gov|National Science Foundation}}** | ||
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