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MQSim is a new simulator that accurately models modern multi-queue SSDs and conventional SATA-based SSDs. A version is available where MQSim is integrated with the gem5 full-system simulator.
Please cite the following accompanying article if you would like to use or build upon the tools:
Arash Tavakkol, Juan Gomez-Luna, Mohammad Sadrosadati, Saugata Ghose, and Onur MutluA processing-in-memory simulator, which was used to model GRIM-Filter.
Please cite the following accompanying article if you would like to use or build upon the tools:
Jeremie S. Kim, Damla Senol Cali, Hongyi Xin, Donghyuk Lee, Saugata Ghose, Mohammed Alser, Hasan Hassan, Oguz Ergin, Can Alkan, and Onur MutluThe Github link to the characterization results of modern DRAM devices under reduced-voltage operation in our SIGMETRICS 2017 paper.
Please cite the following accompanying article if you would like to use or build upon the tools:
Kevin Chang, Abdullah Giray Yaglikci, Saugata Ghose, Abhijith Kashyap, Hasan Hassan, Aditya Agrawal, Niladrish Chatterjee, Donghyuk Lee, Mike O'Connor, Onur MutluMosaic is a modification to GPGPUSim that allows execution of concurrent GPGPU applications. Mosaic accurately models virtual-to-physical address translation, TLBs, page tables, and a page table walker.
Please cite the following accompanying article if you would like to use or build upon the tools:
Rachata Ausavarungnirun, Joshua Landgraf, Vance Miller, Saugata Ghose, Jayneel Gandhi, Christopher J. Rossbach, and Onur MutluGPGPUSim-Ramulator modifies GPGPUSim memory hierarchy with Ramulator our cycle-accurate DRAM simulator.
Besides citing GPGPUSim, please cite the following accompanying article if you would like to use or build upon the tools:
Yoongu Kim, Weikun Yang, and Onur MutluSoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API.
Please cite the following accompanying article if you would like to use or build upon the tools:
Hasan Hassan, Nandita Vijaykumar, Samira Khan, Saugata Ghose, Kevin Chang, Gennady Pekhimenko, Donghyuk Lee, Oguz Ergin, and Onur MutluRamulator is an extensible DRAM simulator providing cycle-accurate performance models for a wide variety of standards: DDR3/4, LPDDR3/4, GDDR5, WIO1/2, HBM, SALP, ALDRAM, TL-DRAM, RowClone, and SARP. Ramulator can be run standalone using traces and a simple core model or can be integrated into gem5 to provide fast memory simulation in a full system simulator.
Please cite the following accompanying article if you would like to use or build upon the tools:
Yoongu Kim, Weikun Yang, and Onur MutluRamulator# (pronounced Ramulator sharp) is a fast and flexible memory subsystem simulator implemented in C# that provides cycle-accurate performance models for a wide variety of standards. Ramulator# is the predecessor of Ramulator (see above). Ramulator# includes source code that implements LISA and ChargeCache.
Please cite the following accompanying article if you would like to use or build upon Ramulator#:
Yoongu Kim, Weikun Yang, and Onur MutluPlease also cite one of the following accompanying articles if you would like to use or build upon LISA or ChargeCache:
Kevin K. Chang, Prashant J. Nair, Donghyuk Lee, Saugata Ghose, Moinuddin K. Qureshi, Onur Mutlu,The IMPICA simulator is a tool that is capable of modeling processing in the logic layer of 3D-stacked memory. Within the simulator, we implement our In-Memory Pointer Chasing Accelerator (IMPICA).
Please cite the following accompanying article if you would like to use or build upon the IMPICA simulator:
Kevin Hsieh, Samira Khan, Nandita Vijaykumar, Kevin K. Chang, Amirali Boroumand, Saugata Ghose, Onur Mutlu,The above link provides the full data set for the DRAM latency variation experiments described in our SIGMETRICS 2016 paper:
Kevin K. Chang, Abhijith Kashyap, Hasan Hassan, Saugata Ghose, Kevin Hsieh, Donghyuk Lee, Tianshi Li, Gennady Pekhimenko, Samira Khan, Onur Mutlu,
"Understanding Latency Variation in Modern DRAM Chips: Experimental Characterization, Analysis, and Optimization"
SIGMETRICS, June 2016.
This simulator models Simultaneous Multi Layer Access (SMLA), an energy efficient high bandwidth 3D-stacked memory.
Please cite the following accompanying article if you would like to use or build upon SMLA:
Donghyuk Lee, Saugata Ghose, Gennady Pekhimenko, Samira Khan, Onur Mutlu,ASMSim models multicore systems with a primary focus on the memory hierarchy. It models a trace-based out-of-order core front end and memory scheduling policies like FRFCFS, ATLAS, TCM and slowdown estimation models, ASM and MISE.
Please cite the following accompanying article if you would like to use or build upon ASMSim:
Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri, Arnab Ghosh, Samira Khan, Onur Mutlu,This application suite consists of applications that exercise specific access patterns to stress cache capacity and main memory bandwdth.
Please cite the following accompanying article if you would like to use or build upon Cache-Memory-Hog:
Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri, Arnab Ghosh, Samira Khan, Onur Mutlu,
"The Application Slowdown Model: Quantifying and Controlling the Impact
of Inter-Application Interference at Shared Caches and Main Memory",
MICRO, December 2015.
MemSchedSim models multicore systems, intended primarily for studies on main memory management techniques. It models a trace-based out-of-order core front end and models memory scheduling policies such as FRFCFS, ATLAS, TCM, BLISS.
Please cite the following accompanying article if you would like to use or build upon MemSchedSim:
Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri, Harsha Rastogi, Onur Mutlu,HWASim is a simulator for heterogeneous systems with CPUs and Hardware Accelerators (HWAs). HWASim has a trace-based front-end out-of-order CPU model and a trace-based HWA model. HWASim also provides memory controller models which support a wide variety of memory schedulers, like FRFCFS, Thread Cluster Memory Scheduling (TCM), and DASH.
Please cite the following accompanying article if you would like to use or build upon HWASim:
Hiroyuki Usui, Lavanya Subramanian, Kevin Kai-Wei Chang, and Onur Mutlu,ThyNVM is a gem5-based persistent memory simulator that implements a DRAM+NVM hybrid memory architecture. It embeds a special checkpointing protocol in the memory controller to support software-transparent crash consistency of whole memory data. ThyNVM can be extended to prototype similar hardware protocols and to experiment with upper-layer software stacks.
Please cite the following accompanying article if you would like to use or build upon the tools:
Jinglei Ren, Jishen Zhao, Samira Khan, Jongmoo Choi, Yongwei Wu, and Onur Mutlu.MeDiC is a mechanism that reduces the negative performance impact of memory divergence and cache queuing. MeDiC uses warp divergence characterization to guide three components: (1) a cache bypassing mechanism that exploits the latency tolerance of low cache utility warps to both alleviate queuing delay and increase the hit rate for high cache utility warps, (2) a cache insertion policy that prevents data from high cache utility warps from being prematurely evicted, and (3) a memory controller that prioritizes the few requests received from high cache utility warps to minimize stall time.
Please cite the following accompanying article if you would like to use or build upon the tools:
Rachata Ausavarungnirun, Saugata Ghose, Onur Kayiran, Gabriel H. Loh, Chita R. Das, Mahmut T. Kandemir, Onur MutluOSS is a dynamic-programming based, linear average-case complexity algorithm that enhances the performance of seed-and-extend based read mappers. OSS finds the least frequent set of e+1 non-overlapping seeds from a read to tolerate a maximum of e errors.
Please cite the following accompanying article if you would like to use or build upon the tools:
Hongyi Xin, Richard Zhu, Sunny Nahar, John Emmons, Gennady Pekhimenko, Carl Kingsford, Can Alkan, Onur MutluThis DRAM error model was developed to help predict the failure rate of servers using data collected across all of Facebook's servers over an 18-month period. It shows how the predicted server failure rate changes over time for servers of a given set of characteristics.
Please cite the following accompanying article if you would like to use or build upon the tools:
Justin Meza, Qiang Wu, Sanjeev Kumar, and Onur MutluNOCulator is an network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, hierarchical ring, flattened butterfly) and routers (buffered, bufferless, Adaptive Flow Control, minBD, HiRD).
Please cite the following accompanying articles if you would like to use or build upon the tools:
Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Chang, Greg Nazario, Reetuparna Das, Gabriel Loh, and Onur Mutlu,Shifted Hamming Distance is a edit-distance based filter that aims to find string pairs with low edit distances.
Please cite the following accompanying articles if you would like to use or build upon the tools:
Hongyi Xin, John Greth, John Emmons, Gennady Pekhimenko, Carl Kingsford, Can Alkan, and Onur MutluThe above link provides the full data sets for the DRAM timing parameter experiments described in our following HPCA 2015 paper:
Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Khan, Vivek Seshadri, Kevin Chang, and Onur Mutlu,
"Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case"
Proceedings of the 21st International Symposium on High-Performance Computer Architecture (HPCA), Bay Area, CA, February 2014.
sirFAST is designed to map short reads generated with the Compelete Genomics (CG) platform to reference genome assemblies in a fast and memory-efficient manner.
Please cite the following accompanying articles if you would like to use or build upon the tools:
Donghyuk Lee, Farhad Hormozdiari, Hongyi Xin, Faraz Hach, Onur Mutlu, and Can Alkan,RowHammer is a memory tester for DRAM disturbance errors. Built on top of Memtest86+ v5.01, it repeatedly activates a DRAM row to induce errors in adjacent rows. It also provides the accompanying data set for our ISCA paper.
Yoongu Kim, Ross Daly, Jeremie Kim, Chris Fallin, Ji Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur MutluMem-Sim is a fast and flexible memory subsystem simulator. The goal of the simulator is to enable ease of simulating many different memory system configurations (primarily the cache). The simulator can be attached to any front-end CPU model. In this code base, we have a simple trace-based front-end Out-of-Order CPU model. Please take a look at the README file for more details.
Please cite the following accompanying articles if you would like to use or build upon the tools:
Vivek Seshadri, Onur Mutlu, Michael A. Kozuch, and Todd C. Mowry,The above link provides the source code for the compression algorithm described in our following PACT 2012 paper:
Important notice for mrFAST users: mrFAST with FastHASH (post 2.5.0.0) is drastically faster than plain mrFAST (pre 2.5.0.0). When using mrFAST, please ensure the version is after 2.5.0.0.
Click here to download the latest version of mrFAST.
Please cite the following accompanying articles if you would like to use or build upon the tools:The above link provides the full data sets for the DRAM retention time experiments described in our following SIGMETRICS 2014 paper:
Samira Khan, Donghyuk Lee, Yoongu Kim, Alaa Alameldeen, Chris Wilkerson, and Onur Mutlu,
"The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study"
Proceedings of the ACM International Conference on Measurement and Modeling of Computer Systems
(SIGMETRICS), Austin, TX, June 2014.