Publications 1990s

Book/Chapter

  1. D. E. Setliff and R. A. Rutenbar, Automatic Programming Applied to VLSI CAD Software: A Case Study, Kluwer Academic Publishers, Boston, MA, 1990. ISBN: 0792391128.
  2. J.M. Cohn, D.J. Garrod, R.A. Rutenbar and L.R. Carley, Analog Device-Level Layout Automation, 285 pp., Kluwer Academic Publishers, Boston, MA, 1994. ISBN: 0-7923-9431-3.
  3. L. R. Carley, P. C. Maulik, E. S. Ochotta, and R. A. Rutenbar, “Analog Cell-Level Synthesis Using a Novel Problem Formulation,” Analog Circuit Design--Operational Amplifiers, Analog to Digital Convertors, Analog Computer Aided Design, Johan H. Huijsing, Rudy J. van de Plassche, Willy M.C. Sansen, eds., Boston, MA: Kluwer Academic Press, Dec. 1992, ISBN: ISBN 0-7923- 9288-4.
  4. B.R. Stanisic, R.A. Rutenbar and L.R. Carley, Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs, Kluwer Academic Publishers, Norwell: MA, 1996. ISBN: 0792397347.
  5. 5. Emil S. Ochotta, Tamal Mukherjee, Rob A. Rutenbar, L. Richard Carley, Practical Synthesis of High-Performance Analog Circuits, Kluwer Academic Publishers, Boston: MA, 1998. ISBN: 0792382374.
  6. R. A. Rutenbar, L.R. Carley, et al., “Synthesis and Layout for Analog and Mixed Signal ICs in the ACACIA System,” in Analog Circuit Design--Low-Noise, Low-Power, Low-Voltage; Mixed- Mode Design with CAD Tools; Voltage, Current and Time References, Johan H. Huijsing, Rudy J. van de Plassche, Willy M.C. Sansen, eds., Kluwer Academic Publishers, Boston: MA, December 1995, ISBN: 0-7923-9659-6.

Journal

  1. J. Cohn, D. Garrod, R. A. Rutenbar and L. R. Carley, “KOAN / ANAGRAM II: New Techniques for Device-Level Analog Placement and Routing,” IEEE Journal of Solid State Circuits, vol. 26, no. 3, February 1991.
  2. D. Setliff and R. A. Rutenbar, “On the Feasibility of Synthesizing CAD Software From Specifications: Generating Maze-Routers in ELF,” IEEE Transactions on CAD of ICs and Systems, vol. 10, no. 6, June 1991.
  3. S.A. Kravitz, R.E. Bryant and R.A. Rutenbar, “Massively Parallel Switch-Level Simulation: A Feasibility Study,” IEEE Transactions on CAD of ICs and Systems, vol. 10, no. 7, June 1991.
  4. D. Setliff and R. A. Rutenbar, “Knowledge Representation and Reasoning in a Software Synthesis Architecture,” IEEE Transactions on Software Engineering, vol. 17, no. 6, June 1992.
  5. B.R. Stanisic, N.K. Verghese, D.J. Allstot, R.A. Rutenbar, L.R. Carley, “Addressing Substrate Coupling in Mixed-Mode ICs: Simulation and Power Distribution Synthesis,” IEEE Journal of Solid State Circuits, vol 29, no. 3, March 1994.
  6. P.C. Maulik, L.R. Carley and R.A. Rutenbar “Simultaneous Topology Selection and Sizing of Cell- level Analog Circuits,” IEEE Transactions on Computer Aided Design, vol. 14, no. 4, April 1995.
  7. B.R. Stanisic, R.A. Rutenbar and L.R. Carley, “Mixed-Signal Noise Decoupling via Simultaneous Power Distribution Design and Cell Customization in RAIL,” IEEE Journal of Solid State Circuits, vol. 30, no. 3, March 1995.
  8. S. Mitra, R.A. Rutenbar, L.R. Carley and D.J. Allstot, “Substrate-Aware Mixed-Signal Macro-Cell Placement in WRIGHT,” IEEE Journal of Solid State Circuits, vol. 30, no. 3, March 1995.
  9. S.W. Director, P.K. Khosla, R.A. Rohrer, R.A. Rutenbar, “Reengineering the Curriculum: Design and Implementation of a New B.S. Degree in Electrical and Computer Engineering at Carnegie Mellon,” Proceedings of the IEEE, vol. 83, no. 9, September 1995.
  10. E.S. Ochotta, R.A. Rutenbar and L.R. Carley, “ASTRX/OBLX: Tools for Rapid Synthesis of High- Performance Analog Circuits,” IEEE Transactions on CAD, vol. 15, no. 3, March 1996.
  11. Glenn Wood and Rob A. Rutenbar, “FPGA Routing and Routability Estimation via Boolean Satisfiability,” IEEE Transactions on VLSI, vol. 6, no. 2, June 1998.
  12. Sudip K. Nag and Rob A. Rutenbar, “Performance-Directed Simultaneous Placement and Routing for FPGAs,” IEEE Transactions on CAD, vol. 17, no. 6, June 1998.
  13. Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley “Transistor-Level Early Floorplanning Algorithms for RF Circuits,” IEEE Transactions on CAD, March 1999.

Conference/Symposium

  1. J. Cohn, D. Garrod, R. A. Rutenbar and L. R. Carley, “New Algorithms for Placement and Routing of Custom Analog Cells in ACACIA,” in Proceedings IEEE Custom Integrated Circuits Conference (CICC’90), May 1990.
  2. E. C. Carlson and R. A. Rutenbar, “Design and Performance Evaluation of New Massively Parallel Mask Verification Algorithms in JIGSAW,” Proceedings 27th ACM/IEEE Design Automation Conference, June 1990.
  3. J. Cohn, D. Garrod, R. A. Rutenbar and L. R. Carley, “KOAN/ANAGRAM II: Flexible Algorithms for Layout of Custom Analog Cells,” Extended Abstract Volume, Semiconductor Research Corporation TECHCON’90, October, 1990.
  4. E. Ochotta, P.C. Maulik, T. Mukherjee, H. Malik, L.R. Carley, and R.A. Rutenbar, “The Evolution of the OASYS Analog Synthesis Tool,” Extended Abstract Volume, Semiconductor Research Corporation TECHCON’90, October, 1990.
  5. J. Cohn, D. Garrod, R. A. Rutenbar, and L. R. Carley, “Techniques for Simultaneous Placement and Routing of Custom Analog Cells in KOAN/ANAGRAM II,” Proceedings 1991 IEEE International Conference on Computer Aided Design (ICCAD’91), Nov. 1991.
  6. R. Jayaraman and R. A. Rutenbar, “A Parallel Steiner Heuristic for Wirelength Approximation of Large Net Populations,” Proceedings 1991 IEEE International Conference on Computer Aided Design (ICCAD’91), Nov. 1991.
  7. E. Ochotta, R.A. Rutenbar and L.R. Carley, “Equation-Free Synthesis of High-Performance Linear Analog Circuits,” in Advanced Research in VLSI and Parallel Systems, T. Knight and J. Savage (eds.), pp. 129-146, Cambridge MA, MIT Press, March 1992.
  8. L. R. Carley, P. C. Maulik, E. S. Ochotta, and R. A. Rutenbar, “Analog Cell-Level Synthesis Using a Novel Problem Formulation,” Proceedings of Workshop on Advances in Analog Circuit Design, T. U. Delft, The Netherlands, April 1992.
  9. P.C. Maulik, L.R. Carley, R.A. Rutenbar, “A Mixed-Integer Nonlinear Programming Approach to Analog Circuit Synthesis,” Proceedings ACM/IEEE Design Automation Conference, June 1992.
  10. S. Mitra, S.K. Nag, R.A. Rutenbar and L.R. Carley, “System-Level Routing of Mixed-SIgnal ASICs in WREN,” Proceedings ACM/IEEE International Conference on CAD (ICCAD’92), November 1992.
  11. B. R. Stanisic, R. A. Rutenbar and L. Richard Carley, “Power Distribution Synthesis for Analog and Mixed-Signal ASICs in RAIL,” Proceedings of the 1993 Custom Integrated Circuits Conference (CICC), May 1993.
  12. R. A. Rutenbar, “Analog Design Automation: Where are We? Where are we Going?” in Proceedings of the 1993 Custom Integrated Circuits Conference (CICC), May 1993 (invited).
  13. E.S. Ochotta, R.A. Rutenbar and L.R. Carley, “Bridging the Gap Between Analog Designers and Analog Synthesis Tools with ASTRX/OBLX,” Extended Abstract Volume, Semiconductor Research Corporation TECHCON’93, Sept. 1993.
  14. S. Mitra, B. Basaran, S.K. Nag, B.R. Stanisic, “Analog and Mixed-Signal Layout at CMU: From Cells to Systems,” Extended Abstract Volume, Semiconductor Research Corporation TECHCON’93, Sept. 1993.
  15. B. Basaran, R.A. Rutenbar and L.R. Carley, “Latchup-Aware Placement and Parasitic-Bounded Routing of Custom Analog Cells,” Proceedings ACM/IEEE International Conference on CAD, November 1993.
  16. B.R. Stanisic, R.A. Rutenbar and L.R. Carley, “Mixed-Signal Noise Decoupling via Simultaneous Power Distribution Design and Cell Customization in RAIL,” Proceedings 1994 IEEE Custom Integrated Circuits Conference, May 1994.
  17. S. Mitra, R.A. Rutenbar, L.R. Carley and D.J. Allstot, “Substrate-Aware Mixed-Signal Macro-Cell Placement in WRIGHT,” Proceedings 1994 IEEE Custom Integrated Circuits Conference, May 1994.
  18. E.S. Ochotta, L.R. Carley and R.A. Rutenbar “Analog Circuit Synthesis for Large, Realistic Cells: Designing a Pipelined A/D Converter with ASTRX/OBLX,” Proceedings IEEE Custom Integrated Circuits Conference, May 1994.
  19. E.S. Ochotta, R.A. Rutenbar and L.R. Carley, “ASTRX/OBLX: Tools for Rapid Synthesis of High- Performance Analog Circuits,” Proceedings 31st ACM/IEEE Design Automation Conference, June 1994.
  20. S.K. Nag and R.A. Rutenbar, “Performance-Directed Simultaneous Place and Route for Row-Based FPGAs,” Proceedings 1994 ACM/IEEE Design Automation Conference, June 1994.
  21. P. Nag, J. Khare, S. Mitra, W. Maly and R.A. Rutenbar, “A Testability Oriented Channel Router,” in Proc. 1995 Indian VLSI Conference, India, Jan. 1995.
  22. R. A. Rutenbar and L.R. Carley, et al., “Synthesis and Layout for Analog and Mixed Signal ICs in the ACACIA System,” Proc. Advances in Analog Circuit Design Workshop, April 1995.
  23. L.R. Carley, R. A. Rutenbar, et al., “Synthesis of High Performance Analog Cells in ASTRX OBLX,” Proc. Systematic Analog Design II Workshop, June 1995.
  24. L.R. Carley, R. A. Rutenbar, et al., “Optimization-based Layout of Analog ICs,” Proc. Systematic Analog Design II Workshop, Leuven, Belgium, June 1995.
  25. S. Mitra, R.A. Rutenbar, L.R. Carley and D.J. Allstot, “A Methodology for Rapid Estimation of Substrate-Coupled Switching Noise,” in Proc. 1995 IEEE Custom IC Conference, May 1995.
  26. S.K. Nag and R.A. Rutenbar, “Performance-Directed Simultaneous Place and Route for Island-Style FPGAs,” Proc. 1995 ACM/IEEE International Conference on CAD, November 1995.
  27. Bulent Basaran and Rob A. Rutenbar, “Efficient Area Minimization for Dynamic CMOS Circuits,” Proc. IEEE Custom IC Conference, May 1996.
  28. Pascal Meier, Rob A. Rutenbar and L. Richard Carley, “Exploring Multiplier Architecture and Layout for Low Power,” Proc. IEEE Custom IC Conference, May 1996.
  29. Bulent Basaran and Rob A. Rutenbar, “An O(n) Algorithm for Optimum CMOS Device Stacking with Analog Constraints,” Proc. ACM/IEEE Design Automation Conference, June 1996.
  30. L. Richard Carley, Georges Gielen, Rob A. Rutenbar, Willy Sansen, “Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend Strategies,” tutorial paper in Proc. 1996 ACM/IEEE Design Automation Conference, June 1996.
  31. Bulent Basaran and Rob A. Rutenbar, “An O(n) Algorithm for Transistor Stacking with Performance Constraints,” Proc. ACM Physical Design Workshop, April 1996.
  32. Bulent Basaran and Rob A. Rutenbar, “Efficient Area Minimization for Dynamic CMOS Circuits,” Proc. ACM Physical Design Workshop, April 1996.
  33. A. Kolli, J. Cagan, and R. A. Rutenbar, “Packing of Generic, Three-Dimensional Components Based on Multi-Resolution Modeling,” Proc. 1996 ASME Design Automation Conference, August 1996.
  34. R. Glenn Wood and Rob A. Rutenbar, “FPGA Routing and Routability Estimation via Boolean Satisfiability,” Proc. ACM International Symposium on FPGAs, February 1997.
  35. Gary Ellis, Lawrence Pileggi and Rob A. Rutenbar, “A Hierarchical Decomposition Methodology for Single-Stage Clock Circuits,” in Proc. 1997 IEEE Custom Integrated Circuits Conference, May 1997.
  36. Gary Ellis, Lawrence Pileggi and Rob A. Rutenbar, “A Hierarchical Decomposition Methodology for Multi-Stage Clock Circuits,” in Proc. 1997 ACM/IEEE International Conference on CAD, november 1997.
  37. Mehmet Aktuna, Rob A. Rutenbar and L. Richard Carley, “Device Level Early Floorplanning for RF Circuits,” in Proc. 1998 ACM International Symposium on Physical Design, April 1998.
  38. Ying-Fai Tong, Rob A. Rutenbar, David Nagle, “Minimizing Floating Point Power Dissipation via Bitwidth Reduction,” Proceedings Power-Driven Microarchitecture Workshop, held at ACM International Symposium on Computer Architecture, 1998.
  39. Michael Krasnicki, Rodney Phelps, Rob A. Rutenbar, L. Richard Carley “Generalized Analog Circuit Synthesis,” Semiconductor Research Corporation TECHCON'98 Conference (abstracts), September 1998.
  40. Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley, “A Layout Approach for RF Circuits with Tight Constraints,” Semiconductor Research Corporation TECHCON'98 Conference (abstracts), September 1998.
  41. Gi-Joon Nam, Karem Sakallah, Rob A. Rutenbar, “Satisfiability-Based Detailed FGPA Routing,” in Proc. International Conference on VLSI, January 1999.
  42. Gi-Joon Nam, Karem Sakallah, Rob A. Rutenbar, “Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs Via Search-Based SAT,” in Proc. ACM International Symposium on FPGAs, February 1999.
  43. Michael Krasnicki, Rodney Phelps, Rob A. Rutenbar, L. Richard Carley “MAELSTROM: Efficient Simulation-Based Synthesis for Custom Analog Cells,” in Proc. ACM/IEEE Design Automation Conference, June 1999.
  44. Rodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, J.R. Hellums, “ANACONDA: Robust Synthesis of Analog Circuits Via Stochastic Pattern Search,” in Proc. IEEE Custom Integrated Circuits Conference, May 1999.
  45. Pascal Meier, Rob A. Rutenbar, L. Richard Carley, “Inverse Polarity Techniques for High-Speed/ Low-Power Multipliers,” Proc. International Symposium on Low-Power Electronics and Design, August 1999.

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