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seminars:towards_rapid_chip_development_with_celerity_and_brgtc1 [2018/04/21 19:38]
jiyuanz created
seminars:towards_rapid_chip_development_with_celerity_and_brgtc1 [2018/05/02 21:28] (current)
jiyuanz
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-Towards Rapid Chip Development with Celerity and BRGTC1 ​+=====Towards Rapid Chip Development with Celerity and BRGTC1=====
  
 +Wednesday April 25, 2018\\
 +Location: CIC Panther Hollow Conference Room\\
 +Time: 4:30PM\\
 +
 +======Abstract=====
 Celerity is a 5x5mm 385M-transistor accelerator-centric SoC in TSMC 16nm technology designed and implemented by a large team of over 20 students and faculty from UC San Diego, U of Michigan, and Cornell as part of the DARPA Circuit Realization At Faster Timescales (CRAFT) program. The goal for the chip was to develop and test new methodologies for rapid chip development in both industry and academia. The chip includes a fully synthesizable PLL, digital LDO, five modified Chisel-generated RISC-V Rocket cores, a 496-core RISC-V tiled manycore processor, tightly integrated Rocket-to-manycore communication channels, complex HLS-generated BNN (binarized neural network) accelerator,​ manycore-to-BNN high-speed links, sleep-mode 10-core manycore, top-level bus interconnect,​ high-speed source-synchronous off-chip I/O, and a custom flip-chip package. Celerity is likely the most complex SoC developed to date in academia. Celerity is a 5x5mm 385M-transistor accelerator-centric SoC in TSMC 16nm technology designed and implemented by a large team of over 20 students and faculty from UC San Diego, U of Michigan, and Cornell as part of the DARPA Circuit Realization At Faster Timescales (CRAFT) program. The goal for the chip was to develop and test new methodologies for rapid chip development in both industry and academia. The chip includes a fully synthesizable PLL, digital LDO, five modified Chisel-generated RISC-V Rocket cores, a 496-core RISC-V tiled manycore processor, tightly integrated Rocket-to-manycore communication channels, complex HLS-generated BNN (binarized neural network) accelerator,​ manycore-to-BNN high-speed links, sleep-mode 10-core manycore, top-level bus interconnect,​ high-speed source-synchronous off-chip I/O, and a custom flip-chip package. Celerity is likely the most complex SoC developed to date in academia.
  
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-Bio:+ 
 +======Bio======
 Christopher Torng is a Ph.D. candidate in the Computer Systems Laboratory at Cornell University. His research interests are in the areas of computer architecture and VLSI, and he is also particularly interested in the challenge of productive hardware design for computer architecture researchers. His recent research spans a range of topics including work-stealing runtimes, heterogeneous big.LITTLE systems, SIMT-like architectures,​ and integrated voltage regulation. Christopher Torng is a Ph.D. candidate in the Computer Systems Laboratory at Cornell University. His research interests are in the areas of computer architecture and VLSI, and he is also particularly interested in the challenge of productive hardware design for computer architecture researchers. His recent research spans a range of topics including work-stealing runtimes, heterogeneous big.LITTLE systems, SIMT-like architectures,​ and integrated voltage regulation.
  
 In the past, he was the student lead at Cornell for the accelerator-centric Celerity SoC in TSMC 16nm, he was the project lead for the BRGTC1 chip in IBM 130nm designed using a Python-based hardware modeling language, and he has also supported the design of two chips in TSMC 65nm and TSMC 180nm with circuits targeting challenges in IoT synchronization and on-chip voltage regulation. In the past, he was the student lead at Cornell for the accelerator-centric Celerity SoC in TSMC 16nm, he was the project lead for the BRGTC1 chip in IBM 130nm designed using a Python-based hardware modeling language, and he has also supported the design of two chips in TSMC 65nm and TSMC 180nm with circuits targeting challenges in IoT synchronization and on-chip voltage regulation.