Friday Dec. 11, 2015
The idea of dynamically reconfiguring programmable devices fascinated Turing in the 1930′s. In the early 90′s, DeHon pioneered dynamic reconfiguration within FPGAs, but neither his nor numerous subsequent efforts, both academic and industrial, resulted in a useful and usable product. During Tabula’s existence, we significantly advanced the hardware, architecture, and software for rapidly reconfiguring, programmable logic: going beyond the FPGA using a body of technology called Spacetime. Spacetime represents two spatial dimensions and one time dimension as a unified 3D framework: a powerful simplification that enabled us to deliver in production a new category of programmable devices (3PLDs) that are far denser, faster, and more capable than FPGAs yet still accompanied by software that automatically maps traditional RTL onto these exotic fabrics. In developing Spacetime, we encountered and resolved many complex, technical challenges that any dense and high-performance reconfigurable device must face, many of which seem never even to have been identified, much less addressed, by any prior effort. In this talk, I will identify some key limitations of FPGAs, introduce Spacetime as a means of addressing them, enumerate some of the many challenges we faced, and present solutions to a couple of them.
Adam Hartman is currently a Member of the Technical Staff at Altera/Intel, where he works on RTL synthesis algorithms for the next-generation Stratix10 FPGA fabric. Prior to Altera/Intel, Adam was a Senior R&D engineer at Tabula, where he worked on RTL synthesis and Tabula’s novel debugging flow called DesignInsight. Adam has also worked on design partitioning for FPGA-based emulators at Synopsys and software testing frameworks at Microsoft. Adam received his B.S. degree in Electrical and Computer Engineering from Carnegie Mellon University in 2006 and is also completing his Ph.D. there.