Diagnostic tools are used to determine the source of failure inside a faulty chip. This project focuses on test-set ordering for maximum diagnosis resolution in chip test data analysis. The aim of the project is to figure out an optimal algorithm for ordering test-sets in order to extract the most valuable information from the resulting test data, with the given test-sets. Thus, the goal is to examine whether ordering test-sets a certain way will contribute to diagnostic resolution improvement.
In this work, several algorithms for reordering test-sets have been developed last semester, along with different metrics to measure and compare the reorderings from different algorithms. These algorithms were applied to reorder test-sets for different benchmark circuits, and the reordered test-sets showed better results according to the metrics as compared to the default ordering from the ATPG used and a significant number of random orderings.
The goal this semester is to apply the developed algorithms to test-sets for large industrial circuits, in order to observe improved diagnosis resolution.