February 24, 2011
Two research papers co-authored by Assistant Professor of ECE Onur Mutlu have been published in a collection of 2010's most significant computer architecture papers, as chosen by IEEE Micro magazine. At the beginning of each year, the leading IEEE periodical in computer architecture and design selects 10-12 "Top Pick" computer architecture papers of the past year based on the publication's novelty and potential for long-term impact. Mutlu's papers - among the 11 selected for 2010 - both tackle the problem of designing more scalable and efficient multicore systems.
The first publication, "Aergia: Exploiting Packet Latency Slack in On-Chip Networks," highlights more efficient on-chip communication mechanisms. It introduces methods that identify messages critical for system performance in multicore systems and develops scheduling policies that take advantage of this information. The paper - co-written by Mutlu, Reetuparna Das (Intel), Chita Das (Penn State University), and Thomas Moscibroda (Microsoft Research) - originally appeared at the 37th International Symposium on Computer Architecture (ISCA). The Top Picks version of the paper is available here.
In the second Top Pick, "Data Marshaling for Multicore Architectures," Mutlu and colleagues from the HPS Research Group at the University of Texas at Austin develop hardware/software cooperative methods to reduce the performance overhead of remotely executing a code segment in a multicore system. The paper, co-written by Aater Suleman, Jose Joao, Khubaib, and Yale Patt, also originally appeared at the 37th ISCA. The Top Picks version of the paper is available here.
For more on Mutlu's work, visit www.ece.cmu.edu/~safari/.
Assistant Professor of ECE Onur Mutlu