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Owing to random events of a diverse nature, only a fraction of fabricated integrated circuits (ICs) meet required specifications. The objective of this research is to study and model all major physical phenomena that cause IC manufacturing failures. These models are then applied to develop design and process modification, minimizing chances of IC malfunctions.
Recent progress in integrated circuit (IC) technology allows for integration of the entire electronic system in a single silicon chip. The strategy of the integration involves a number of complex trade-offs. The objective of this project is to identify and quantify these trade-offs, as well as develop a prototype computer tool enabling navigation in the complex system integration design space.
Effective design for manufacturability methodology must use adequate information about process-generated defects. The objective of this project is to study new VLSI design and test methodologies that enable better defect observability via interpretation of test results. New current signature and DFT of embedded memories-based methods are employed to achieve the defect observability objectives.