Carnegie Mellon University

Wojciech Maly

Wojciech Maly

Professor Emeritus, Electrical and Computer Engineering

Address 5000 Forbes Avenue
Pittsburgh, PA 15213


Wojciech Maly received the M.Sc. degree in electronic engineering from the Technical University of Warsaw, Poland, in 1970, and the Ph.D. degree from the Institute of Applied Cybernetics, Polish Academy of Sciences, Warsaw, Poland, in 1975. From 1970 to 1973, he was with the Institute of Applied Cybernetics. In 1973, he joined the Technical University of Warsaw, where he was appointed Assistant Professor in 1975. From September 1979 to July 1981, he was a Visiting Assistant Professor of Electrical and Computer Engineering at Carnegie Mellon University, Pittsburgh, PA. Since September 1983, he has been with Carnegie Mellon University, where he is a Whitaker Professor of Electrical and Computer Engineering.

Dr. Maly's research interests have been focused on the interfaces between VLSI design, testing and manufacturing with the stress on the stochastic nature of phenomena relating these three VLSI domains. He has authored, co-authored and edited a number of books, journal and conferences papers, as well as patents, which have attempted to promote integration of design, test and manufacturing. Among his publications addressing the above field are papers introducing: statistical process simulation, layout-oriented yield modeling, defect-based approaches to fault modeling (including inductive fault analysis) as well as new design for manufacturability CAD strategies and defect/quality oriented testing methodologies.

Dr. Maly was elected an IEEE Fellow in 1990 and has been recipient or co-recipient of various awards including honors for his Ph.D. thesis, Ministry of Higher Education of Poland Research Award, Carnegie Mellon's Benjamin Richard Teare Teaching Award, AT&T Foundation Award for Excellence in Instructing of Engineering Students, Fellowship from Deutsche Forschungsgemeinschaft, SRC 1992 Technical Excellence Award, Best Paper Award from the International Test Conference 1990, the Best Paper Award from ESREF 94 , the 1994 Best Paper Award from IEEE Transaction on Semiconductor Manufacturing, 1995 Best Paper Award from 1996 European Design and Test Conference and Eta Kappa Nu CMU Sigma Chapter Excellence in Teaching Award.


PhD, 1975 
Electrical and Computer Engineering 
Polish Academy of Sciences

MS, 1970 
Electrical and Computer Engineering 
Technical University of Warsaw


Circuit and Process Design for IC Manufacturability

Owing to random events of a diverse nature, only a fraction of fabricated integrated circuits (ICs) meet required specifications. The objective of this research is to study and model all major physical phenomena that cause IC manufacturing failures. These models are then applied to develop design and process modification, minimizing chances of IC malfunctions.

Silicon Implementation Strategy Advisor

Recent progress in integrated circuit (IC) technology allows for integration of the entire electronic system in a single silicon chip. The strategy of the integration involves a number of complex trade-offs. The objective of this project is to identify and quantify these trade-offs, as well as develop a prototype computer tool enabling navigation in the complex system integration design space.

Design and Test for Defect Observability

Effective design for manufacturability methodology must use adequate information about process-generated defects. The objective of this project is to study new VLSI design and test methodologies that enable better defect observability via interpretation of test results. New current signature and DFT of embedded memories-based methods are employed to achieve the defect observability objectives.