Welcome to my ECE web site

I am currently a doctoral student in the Dept. of Electrical and Computer Engineering at Carnegie Mellon University. I'm persuing my Ph.D. under the guidance Prof. Wojciech Maly in the field of test-based characterization of manufacturing process deformations of nano-scale integrated circuits (ICs). I am part of the Design, Test and Manufacturing Interfaces group and also strongly involved in the research activities of the Carnegie Mellon Laboratory for Integrated Systems Test (CM-LIST) group. Both groups are affiliated to the Center for Silicon System Implementation (CSSI).

My research interest

It is a well-known fact that good understanding of failure mechanisms and thorough characterization of manufacturing process deformations are essential components for fast-ramping nano-scale integrated circuit (IC) fabrication. The procedure carried out to attain these goals is commonly referred to as IC failure analysis.

Recent developments throughout the IC manufacturing industry have clearly shown that IC failure analysis is becoming increasingly more difficult to conduct efficiently. With every emerging IC process technology a myriad of new failure mechanisms and other process-related issues have to be faced - primarily driven by the continuous miniaturization of integrated circuit devices and the growing complexity of manufacturing processes.

The guiding theme of my Ph.D. research is therefore to investigate and develop new IC failure analysis strategies that maximize IC manufacturing process deformation learning with minimum effort to the IC manufacturer. Their intended purpose is not to fully replace, but to complement and enhance existing traditional IC failure analysis techniques. In line with the thrust of my research groups, I focus predominantely on investigating methodologies that enable effcient deformation characterization based on the analysis of electrical test results from failing or otherwise misbehaving integrated circuits.