Yen-Tzu Lin

I am a PhD candidate in Electrical and Computer Engineering at Carnegie Mellon University. I am a member of Advanced Chip Test Laboratory, advised by Prof. Shawn Blanton. Before coming to CMU, I worked for Richtek in the circuit design group and prior to that I worked in computer-aided design for EE Solutions, Inc. I received my B.S. and M.S. in Electrical Engineering from National Tsing Hua University (NTHU), Taiwan. I was with the Laboratory of Reliable Computing (LaRC), NTHU.

Research

My research interests include various aspects of VLSI testing and design. My current research focuses on test methodology development and evaluation. I have developed a cost-effective test methodology that creates high-quality test sets capable of improving defect detection for modern designs. The methodology has been applied on an IBM in-production ASIC, and the generated test set achieves a defect level reduction of 30 DPPM (defect parts per million). My current work involves improving the efficiency and applicability of the developed test methodology through utilization of GPUs.

I have also developed a novel test evaluation methodology that assesses the effectiveness of test and design-for-testability (DFT) methods. The methodology has been applied to evaluate some new and existing test methods using test-measurement data from real silicon.

Publications

Y.-T. Lin and R. D. Blanton, “Test Effectiveness Evaluation through Analysis of Readily-Available Tester Data,” International Test Conference, November 2009
Y.-T. Lin, O. Poku, N. K. Bhatti, R. D. Blanton, “Physically-Aware N-Detect Test Pattern Selection,” ACM Design and Test in Europe, March 2008.
Y.-T. Lin, O. Poku, R. D. Blanton, Phil Nigh, Peter Lloyd, Vikram Iyengar, “Evaluating the Effectiveness of Physically-Aware N-Detect Test using In-Production Silicon,” IEEE International Test Conference, Oct. 2008.
Y.-T. Lin, C. U. Ezekwe, R. D. Blanton, “Physically-Aware N-Detect Test Relaxation,” IEEE VLSI Test Symposium, May 2009.
X. Yu, Y.-T. Lin, R. D. Blanton, “Controlling DPPM through Volume Diagnosis,” IEEE VLSI Test Symposium, May 2009.

Contact

yentzul AT ece DOT cmu DOT edu

Hamerschlag Hall 2136
Department of Electrical and Computer Engineering
Carnegie Mellon University
Pittsburgh, PA 15213
U.S.A.