Technological advancements in semiconductor fabrication have led to an abundance of on-chip transistors, faster clock speeds, and unprecedented processor performance. In contrast, while DRAM capacity has increased commensurately, DRAM speeds have primarily lagged behind resulting in an ever-increasing processor/memory performance gap.

Spatio-Temporal Memory Streaming (STeMS) is a new memory system architecture in which memory moves in correlated groups (called spatio-temporal streams) rather than individual cache blocks to enhance fetch lookahead and memory-level parallelism, hide memory latency, and improve on-chip storage utilization and pin bandwidth.

Our preliminary results indicate that a STEMS-based system can eliminate over 60% of shared cache misses in on-line transaction processing server software.