SLD:: System Level Design Group @ CMU

Embedded systems have become ubiquitous in day-to-day life, and this trend will only continue as advances in semiconductor technology allow for more IP blocks on a single chip and demand for integrated electronics systems increases. Our group focuses on fundamental research issues and state-of-the-art solutions concerning both computation and communication aspects of system-level design in embedded applications.

• R. Marculescu, P. Bogdan, ' The Chip Is the Network: Toward a Science of Network-on-Chip Design', Foundations and Trends in Electronic Design Automation, vol. 2, no. 4, pp. 371-461, March 2009.
• R. Marculescu, U. Y. Ogras, L.-S. Peh, N. E. Jerger, Y. Hoskote, ' Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives ', in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 28, no. 1, pp. 3-21, Jan. 2009.
• R. Marculescu, U. Y. Ogras, N. H. Zamora, ' Computation and Communication Refinement for Multiprocessor SoC Design: A System-Level Perspective , ' in ACM Trans. on Design Automation of Electronic Systems, Special Issue on Novel Paradigms in System-Level Design, Vol.11, No.3, pp. 564-592, July, 2006.

A quantum-leap over classical bus-based designs, Networks-on-Chip allow for scalable multi-processor platforms with hundreds, and soon thousands, of cores. We investigate the fundamental paradigm shift towards network-centric thinking, work to expose the fundamental mathematical patterns that define important classes of on-chip communication, and use these patterns to analyze and optimize these designs

Creating the hardware for scalable multi-processor systems is only half the battle - knowing how to exploit their capabilities is an entirely different matter. Our group explores methods for efficiently mapping applications to parallel platforms, as well as what the data demands of such applications can tell us about how to design better hardware.

With the emergence of Networks-on-Chip and similar-minded platforms, on-chip communication is now a paramount concern. Finding optimal network designs and routing algorithms is a key focus, and we explore topics such as stochastic communication, small world networks, dynamic reconfigurable networks, and fractal behavior/self-similarity.

Another even more fundamental concern, extending beyond just multi-core systems, is energy consumption. Areas of exploration include distributed and centralized control schemes, multi-VFI designs, and power optimization methods to limit energy consumption while preserving performance.

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