Tutorial @ ISCA2010
Multi-domain Processors: Challenges, Design Methods, and Recent Developments
Presenters
Radu Marculescu, Carnegie Mellon Univ.
Ran Ginosar, Technion
Diana Marculescu, Carnegie Mellon Univ.
Stefan Rusu, Intel Corp.
When/Where
This half-day tutorial will be held on the afternoon of Saturday, June 19. The complete workshop and tutorial schedule for ISCA 2010 can be found here.
Abstract
Multi-domain processors characterized by multiple clock/voltage and power domains are widely used to manage power in modern nano-scale processor designs, especially in large scale multi- or many-core systems that require aggressive power management methodologies. One such example is the 48-core prototype processor recently announced by Intel Corp. In order to understand the challenges and opportunities in this problem space, this tutorial presents a comprehensive overview of advanced design techniques in multi-domain clock and power management for high-performance processors, as well as low power systems-on-chip (SoCs).
As the number of components on a single chip and their performance continue to increase, the design of the communication architecture plays a major role. From this perspective, this tutorial addresses the network-on-chip (NoC) design and presents several research issues where the concept of “network” is at the forefront of multi/many-core processing. NoCs are suitable for large high-performance chip multiprocessors as well as SoCs, all of which increasingly employing a multi- domain design style. Consequently, the tutorial surveys asynchronous routers for various architectures and asynchronous interconnections that enable higher bandwidth and lower power. The tutorial will discuss these issues and outline existing approaches to overcome any inherent deficiencies and fully enable the aforementioned technology.
In addition to the on-chip communication problem, the twin concern of increased power consumption of future multi/many-core systems needs to be addressed, especially in the presence of workload and parameter variations. For multi-core designs, the concept of multiple voltage/frequency islands (VFIs) is typically used to enable fine-grain power management. In such a system, each island can work at its own speed, while the communication across different VFIs is achieved through mixed clock/mixed voltage FIFOs. We plan to discuss the design and management of novel NoC architectures partitioned into multiple VFIs, as well as online feedback control mechanisms that can dynamically adjust the operating voltage and frequency around some statically prescribed values.
Finally, considering variability effects at micro-architecture and architecture levels is needed for determining variation-aware dynamic power management algorithms that are most likely to meet performance and power constraints. Towards this end, we plan to discuss modeling the effects of process variation at micro-architecture/architecture level in modern multi/many-core, multi-domain systems and show how dynamic power management mechanisms can be developed such that these systems behave in a robust manner in the presence of process technology parameter variation. Of extreme importance is the ability to provide workload- and process variability-driven adaptability not only through a static assignment of local voltages/frequencies, but also using dynamic application mapping and on-the-fly voltage/frequency scaling.
Topics to be covered
- Multi-Domain Processors Design Overview
- Multi-domain server, cell phone, and media processors
- Clock, data synchronization, power grids
- Test and modular design techniques
- Router Design and Synchronization Issues
- Asynchronous router design
- Quality of Service and virtual channels in QNoC
- Power gating and voltage scaling in asynchronous NoC
- Control and Power Management in Presence of Workload Variations
- Multiple voltage-frequency island (VFI) design
- Workload modeling
- Control of multi-VFI designs and run-time resource management
- Robust Design and DVFS in Presence of Process Variations
- Process variation modeling at micro-architecture/architecture level
- Variation aware dynamic power management of multi-/many-core systems
- Post-manufacturing/test-time voltage/frequency selection under process variations
Duration of the tutorial: 4.5 hours.
Speaker bios
Radu Marculescu is a Professor in the Dept. of Electrical and Computer Engineering at Carnegie Mellon University, USA. He received his Ph.D. in Electrical Engineering from the University of Southern California in 1998. He received the Best Paper Award of IEEE Transactions on VLSI Systems in 2005, as well as several best paper awards in the area of design automation. Dr. Marculescu has been involved in organizing many international symposia, conferences, workshops, and tutorials, as well as guest editor of special issues in archival journals and magazines. His research focuses on design methodologies and software tools for system-on-chip design, on-chip communication, and ambient intelligence. Radu Marculescu is an ACM Distinguished Speaker (2009-2010).
Ran Ginosar received his BSc (summa cum laude) from the Technion in 1978, and his PhD from Princeton University in 1982, both in Electrical and Computer Engineering. He worked at AT&T Bell Laboratories in 1982-1983, and joined the Technion faculty in 1983. He was a visiting Associate Professor with the University of Utah in 1989-1990 and a visiting faculty with Intel Research Labs in 1997-1999. He co-founded several companies in various application areas of VLSI systems. He is an Associate Professor with the Departments of Electrical Engineering and Computer Science and serves as Head of the VLSI Systems Research Center at the Technion. His research interests include VLSI architecture, many-core computers, asynchronous logic and synchronization, and networks on chip.
Diana Marculescu is a Professor of Electrical and Computer Engineering at Carnegie Mellon University. She received her Ph.D. in Computer Engineering from University of Southern California in 1998. She is the recipient of a National Science Foundation Faculty Career Award and Best Paper Awards from IEEE Asia South-Pacific Design Automation Conference, IEEE International Conference on Computer Design, and International Symposium on Quality of Electronic Design. Diana Marculescu was an IEEE-Circuits and Systems Society Distinguished Lecturer, the Chair of the ACM Special Interest Group on Design Automation and is a Senior Member of ACM and IEEE. Her research interests include energy- and reliability-aware computing, CAD tools for low power systems and emerging technologies.
Stefan Rusu received the MSEE degree from the Polytechnic University in Bucharest, Romania. His industry experience includes over 18 years with Intel Corporation and 6 years at Sun Microsystems. He is presently a Senior Principal Engineer in Intel's Enterprise Microprocessor Group leading the technology and special circuits design activities for the Xeon®MP Processors. He has authored over 80 papers on VLSI circuit technology and holds 34 U.S. patents. He is an IEEE Fellow and a member of the Technical Program Committee for ISSCC, ESSCIRC and A-SSCC conferences. Stefan is a Distinguished Lecturer for the IEEE Solid-State Circuits Society and an Associate Editor of the IEEE Journal of Solid-State Circuits.