Tutorial @ ASPLOS 2012
Power Management of Multicore Systems: Challenges, Approaches, and Recent Developments
Presenters
Radu Marculescu, Carnegie Mellon Univ.
Umit Y. Ogras, Intel Corp.
Siddharth Garg, Univ. of Waterloo
When/Where
This full-day tutorial will be held on Sunday, March 4, 2012. The complete workshops and tutorial schedule for ASPLOS 2012 can be found here.
Summary
Continuous technology scaling allows hundreds of processing cores to run multiple heterogeneous applications concurrently on a single chip. However, on-chip power consumption represents one of the main bottlenecks in providing increased performance and enhanced capabilities for such platforms. Indeed, increased power consumption results not only in higher on-die temperature and reduced lifetime reliability, but also leads to faster discharge of battery-powered mobile devices. On-chip power management is therefore a critical component of run time multicore optimization in presence of workload and process-driven variations.
Power management techniques for single core processor are well established. For example, current commercial products support numerous sleep and performance states. However, orchestrating power management policies for processors consisting of many cores interconnected by an on-chip network is much less addressed. The multiple voltage and frequency island (VFI) design style with support for dynamic voltage and frequency scaling (DVFS) was recently proposed as an effective paradigm to deal with application heterogeneity in highly parallel multi-core platforms. Such systems are divided into multiple VFIs where the voltage and frequency of each island in the system can be set independently of all other islands and can be adapted at run-time in response to temporal variations in application characteristics.
Starting from these overarching ideas, this tutorial addresses some fundamental issues of designing effective and highly scalable DVFS control algorithms able to regulate the voltage and frequency of the VFIs in large multi-core platforms in response to application heterogeneity and process-driven variations. In order to understand the challenges and opportunities in this problem space, this tutorial presents a comprehensive review of advanced design techniques for multi-domain power and thermal management for high-performance processors and low power systems-on-chip (SoCs). Finally, we discuss fundamental limits on the performance of such control algorithms for power management due to the challenges introduced by technology scaling and process variations, particularly with respect to emerging thousand core platforms.
Intended Audience
This tutorial is intended for an audience relatively new to the design and optimization techniques for power- and variability-aware design and management of multicore systems, with a minimal background in micro-architecture, VLSI, and design automation techniques. The presentation will introduce the relevant background material, give an overview of the current state-of-the-art results in VFI and Globally Asynchronous Locally Synchronous alternatives for designing the communication infrastructure, and finally, talk about run-time resource optimization and dynamic power management in the presence of workload and parameter variations. The material discussed in this tutorial is highly relevant to system designers and software developers interested in the future of multi- and many-core systems.
Topics to be covered
- Multicore Platforms Overview
- Multi-voltage/clock domain server, cell phone, and media processors
- Network-based communication and multiple voltage-frequency island (VFI) design
- Industrial examples: Intel 80-core design, Intel SCC 48-core, Tilera, etc.
- Control and Power Management: Algorithms and Implementation
- Dynamic control of multi-VFI designs at micro-architecture/OS/application-level
- Centralized, distributed, and hierarchical approaches for power and thermal management
- Implementation complexity and practical evaluations using Intel SCC platform
- DVFS Control in Presence of Process Variations
- Variation-aware dynamic power and thermal management
- Power and thermal management for 3-D architectures
- Scalability and workload challenges for thousand core platforms
Duration of the tutorial: 6 hours, split into several sessions.
Speaker bios
Radu Marculescu is a Professor in the Dept. of Electrical and Computer Engineering at Carnegie Mellon University, USA. He received his Ph.D. in Electrical Engineering from the University of Southern California in 1998. He has received the Best Paper Award of IEEE Trans. on VLSI Systems in 2005 and 2011, as well as several best paper awards in major conferences in the area of design automation. Dr. Marculescu is currently an Associate Editor of IEEE Trans. on Computers, IEEE Trans. on Computer-Aided Design of Circuits and Integrated Systems, and ACM Trans. on Embedded Computing Systems. His research focuses on design methodologies and software tools for system-on-chip design, on-chip communication, and cyber-physical systems.
Umit Y. Ogras is a research scientist in Intel Strategic CAD Labs. He received his Ph.D. degree in Electrical and Computer Engineering at Carnegie Mellon University. He received the 2008 Outstanding Dissertation Awards from the European Design Automation Association (EDAA) and Best Paper Award of IEEE Trans. on VLSI Systems in 2011. His research interests are in the areas of embedded systems and electronic design automation. In particular, his research focuses on communication-centric design methodologies for nanoscale SoCs, with a special interest on Networks-on-Chip communication architectures.
Siddharth Garg is an Assistant Professor in the ECE Department University of Waterloo. Prior to this, he was a post-doctoral research associate at Carnegie Mellon University, where he also received his Ph.D. in Electrical and Computer Engineering in 2009. His Ph.D. thesis at CMU, which won the A.G. Jordan Award for outstanding thesis contributions, proposed new design and analysis methodologies for variation-tolerant digital circuits in nanometer CMOS technologies. His research interests are in the general area of embedded systems, with particular emphasis in 2- and 3D technologies for multicore systems.