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NOCS 2011: Technical Program

Sunday, May 1, 2011: Tutorial Day
9:00 - 9:30 am       Continental Breakfast
9:30 - 12:00 pm     T1 - Many-core Applications Research using the Intel Single-Chip Cloud Computer (SCC)
Tim Matson (Intel Corp)
12:00 - 1:30 pm     Lunch
1:30 - 3:30 pm      T2 - Adaptive Multi-core SoCs: Trends, Challenges and Perspectives
François Pêcheux (UPMC/LIP6, France), Gilles Sassatelli (LIRMM, France), Fabien Clermidy (CEA/LETI, France)
3:30 - 4:00 pm      Break
4:00 - 6:00 pm      T3 - Optical Interconnects for NOCS and Off-chip Communications
Philip Watts (Univ. of Cambridge, UK), Kevin Williams (Eindhoven Univ. of Technology, The Netherlands)
6:30 - 8:30 pm      Welcome Reception
Monday, May 2, 2011
7:45 - 8:15 am      Continental Breakfast
8:15 - 8:30 am      Opening Remarks
8:30 - 9:30 am      Keynote 1 - On-Chip Interconnect in a Tile Manycore Processor: When the Rubber Meets the Road
Anant Agarwal,
Professor of Electrical Engineering and Computer Science, MIT, and Founder and CTO, Tilera Corporation
9:30 - 10:00 am     Coffee Break
10:00 - 12:00 pm    Session 1 - Routing, Congestion Control and Deadlock Avoidance
Session Chairs: Ran Ginosar and Jens Sparsoe
10:00 – 10:30 am    1.1 - Efficient Routing Implementation in Complex Systems-on-Chip Designs
Jose Cano1,  Jose Flich1,  Jose Duato1,  Marcello Coppola2,  Riccardo Locatelli2
1Technical University of Valencia, 2STMicroelectronics
10:30 – 11:00 am    1.2 - Analysis of Application-Aware On-Chip Routing under Traffic Uncertainty
Nithin Michael,  Milen Nikolov,  Ao Tang,  Edward Suh,  Christopher Batten
Cornell University
11:00 – 11:15 am    1.3 - HOPE: Hotspot Congestion Control for Clos Network On Chip (S)
Najla Alfaraj,  Junjie Zhang,  Yang Xu,  H. Jonathan Chao
Polytechnic Institute of New York University
11:15 – 11:30 am    1.4 - Automatic verification for deadlock in networks-on-chips with adaptive routing and wormhole switching (S)
Freek Verbeek1 and Julien Schmaltz2
1Radboud University Nijmegen, 2Open University of The Netherlands
11:30 – 12:00 pm    1.5 - Deadlock-Free Fine-Grained Thread Migration (Best Paper Candidate)
Myong Hyon Cho,  Mieszko Lis,  Keun Sup Shim,  Omer Khan,  Srinivas Devadas
12:00 - 1:30 pm     Lunch
1:30 - 3:30 pm      Session 2 - Flow Control and 3D Networks
Session Chairs: Fabien Clermidy and Jose Flich
1:30 – 2:00 pm      2.1 - Prevention Flow-Control for Low Latency Torus Networks-on-Chip
Arpit Joshi and Madhu Mutyam
IIT Madras
2:00 – 2:30 pm      2.2 - A Vertical Bubble Flow Network using Inductive-Coupling for 3-D CMPs
Hiroki Matsutani1, Yasuhiro Take2, Daisuke Sasaki2, Masayuki Kimura2, Yuki Ono2, Yukinori Nishiyama2,
Michihiro Koibuchi3, Tadahiro Kuroda2, Hideharu Amano2

1The University of Tokyo, 2Keio University, 3National Institute of Informatics
2:30 – 3:00 pm      2.3 - Optimal Network Architectures for Minimizing Average Distance in k-ary n-dimensional Mesh Networks
Matt Grange1,  Roshan Weerasekera1,  Dinesh Pamunuwa1,  Axel Jantsch2,  Awet Yemane Weldezion2
1Lancaster University, 2KTH
3:00 – 3:15 pm      2.4 - Congestion Aware, Fault Tolerant, and Thermally Efficient Inter-Layer Communication Scheme
for Hybrid NoC-Bus 3D Architectures (S)

Amir-Mohammad Rahmani1, Khalid Latif1, Vaddina Kameswar Rao1, Pasi Liljeberg2, Juha Plosila2, Hannu Tenhunen1
1University of Turku and Turku Centre for Computer Science, 2University of Turku
3:15 – 3:30 pm      2.5 - Exploring Partitioning Methods for 3D Networks-on-Chip Utilizing Adaptive Routing Model (S)
Masoumeh Ebrahimi,  Masoud Daneshtalab,  Pasi Liljeberg,  Juha Plosila,  Hannu Tenhunen
University of Turku
3:30 - 4:00 pm      Coffee Break
4:00 - 5:30 pm      Session 3 - Photonic On-Chip Networks
Session Chairs: Luca Carloni and Hiroki Matsutani
4:00 – 4:30 pm      3.1 - BLOCON: A Bufferless Photonic Clos Network-on-Chip Architecture (Best Paper Candidate)
Yu-Hsiang Kao and H. Jonathan Chao
Polytechnic Institute of New York University
4:30 – 5:00 pm      3.2 - Two-Hop Free-Space Based Optical Interconnects for Chip Multiprocessors
Ahmed Abousamra,  Rami Melhem,  Alex Jones
University of Pittsburgh
5:00 – 5:30pm       3.3 - All-optical wavelength-routed NoC based on a novel hierarchical topology
Somayyeh Koohi,  Meisam Abdollahi,  Shaahin Hessabi
Computer Engineering Department, Sharif University of Technology
5:30 - 6:30 pm      Poster Session
Every paper presented during the day will have an accompanying poster.
Tuesday, May 3, 2011
8:00 - 8:30 am      Continental Breakfast
8:30 - 9:30 am      Keynote 2 - Integrating the Network: Why It Matters
Tryggve Fossum,
Director of Microarchitecture Development, Intel
9:30 - 10:00 am     Coffee Break
10:00 - 12:00 pm    Session 4 - Testing and Fault Tolerance
Session Chairs: Steven Nowick and Marly Roncken
10:00 – 10:30 am     4.1 - Exploiting Inherent Information Redundancy to Manage Transient Errors in NoC Routing Arbitration
(Best Paper Candidate)

Qiaoyan Yu,  Meilin Zhang,  Paul Ampadu
University of Rochester
10:30 – 11:00 am     4.2 - A Distributed and Topology-Agnostic Approach for On-line NoC Testing
Mohammad Reza Kakoee1,  Valeria Bertacco2,  Luca Benini1
1University of Bologna, Italy, 2University of Michigan, Ann Arbor, USA
11:00 – 11:30 am    4.3 - Energy and Reliability Oriented Mapping for Regular Networks-on-Chip
Cristinel Ababei1,  Hamed Sajjadi Kia1,  Om Prakash Yadav1,  Jingcao Hu2
1North Dakota State University, 2Tabula Inc.
11:30 – 12:00 pm     4.4 - Online Task Remapping Strategies for Fault-tolerant Network-on-Chip Multiprocessors
Onur Derin,  Deniz Kabakci,  Leandro Fiorin
ALaRI, University of Lugano
12:00 - 1:30 pm     Lunch
1:30 - 3:30 pm      Session 5 - Simulation and Delay Analysis
Session Chairs: Chita Das and Marcello Coppola
1:30 – 2:00 pm       5.1 - FIST: A Fast, Lightweight, FPGA-Friendly Packet Latency Estimator for NoC Modeling in Full-System Simulations
Michael K. Papamichael1,   James C. Hoe2,   Onur Mutlu2
1Computer Science Department, Carnegie Mellon University, 2Electrical and Computer Engineering, Carnegie Mellon University
2:00 – 2:30 pm       5.2 - DART: A Programmable Architecture for NoC Simulation on FPGAs,
Danyao Wang1,  Natalie Enright Jerger2,  J. Gregory Steffan2
1Google, 2University of Toronto
2:30 – 3:00 pm       5.3 - Inferring Packet Dependencies to Improve Trace Based Simulation of On-Chip Networks
Christopher Nitta,  Kevin Macdonald,  Matthew Farrens,  Venkatesh Akella
University of California Davis
3:00 – 3:30 pm       5.4 - Delay Analysis of Wormhole Based Heterogeneous NoC
Yaniv Ben-Itzhak,  Israel Cidon,  Avinoam Kolodny
Electrical Engineering Department Technion – Israel Institute of Technology Haifa, Israel
3:30 - 4:30 pm      Poster Session (along with coffee break)
Every paper presented during the day will have an accompanying poster.
4:30 - 6:00 pm      Special Session 1 - Curbing Energy Cravings in Networks: a Cross-sectional view across the Micro-Macro Boundary
Session Chair: Partha Pande
4:30 – 5:00 pm       S1.1 - Power and Thermal Management for Multi-Core Processors
Pradip Bose
IBM Thomas J. Watson Research Center
5:00 – 5:30 pm       S1.2 - Interconnect-Architecture Co-design for Power Optimization of On-chip Networks
Amlan Ganguly
Rochester Institute of Technology
5:30 – 6:00 pm       S1.3 - Role of NoC in Data Center/Cloud Computing
Partha Kundu
Juniper Networks
7:00 - 10:00 pm     Gala Dinner
Wednesday, May 4, 2011
7:30 - 8:00 am       Continental Breakfast
8:00 - 10:00 am     Session 6 - Wireless and Asynchronous NoC
Session Chairs: John Bainbridge and Cristinel Ababei
8:00 – 8:30 am       6.1 - Complex Network Inspired Fault-Tolerant NoC Architectures with Wireless Links
Amlan Ganguly1,  Paul Wettin2,  Kevin Chang2,  Partha Pande2
1Rochester Institute of Technology, 2Washington State University
8:30 – 9:00 am       6.2 - Design of Multi-Channel Wireless NoC to Improve On-Chip Communication Capacity
Dan Zhao1,  Yi Wang1,  Jian Li2,  Takamaro Kikkawa3
1Univ. of Louisiana at Lafayette, 2IBM Research, 3Hiroshima University
9:00 – 9:30 am       6.3 - Link Pipelining Strategies for an Application-Specific Asynchronous NoC
Daniel Gebhardt,  Junbok You,  Kenneth Stevens
University of Utah
9:30 – 10:00 am      6.4 - A Low-Latency Adaptive Asynchronous Interconnection Network Using Bi-Modal Router Nodes
Gennette Gill,  Sumedh Attarde,  Geoffray Lacourba,  Steven Nowick
Columbia University
10:00 - 10:30 am    Coffee Break
10:30 - 12:30 pm    Session 7 - System-level, Micro-architecture, Circuits and Physical Design
Session Chairs: Diana Marculescu and Andreas Hansson
10:30 – 11:00 am     7.1 - Dynamic Decentralized Mapping of Tree-Structured Applications on NoC Architectures
Andreas Weichslgartner,  Stefan Wildermann,  Jürgen Teich
University of Erlangen-Nuremberg
11:00 – 11:30 am     7.2 - Cross Clock-Domain TDM Virtual Circuits for Networks on Chips
Zhonghai Lu
Royal Institute of Technology (KTH), Sweden
11:30 – 12:00 pm    7.3 - VLSI Micro-Architectures for High-Radix Crossbar Schedulers
Giorgos Passas,  Manolis Katevenis,  Dionisis Pnevmatikatos
12:00 – 12:15 pm     7.4 - Interconnect Physical Analyser (IPAA) applied to the design of scalable Network-on-Chip Interconnect
for Cryptographic Accelerators (S)

Tom English and Emanuel Popovici
University College Cork, Ireland
12:15 – 12:30 pm     7.5 - Reducing Network-on-Chip Energy Consumption Through Spatial Locality Speculation (S)
Hyungjun Kim1,  Pritha Ghoshal1,  Boris Grot2,  Paul V. Gratz1,  Daniel A. Jimenez3
1Texas A&M University, 2University of Texas at Austin, 3University of Texas at San Antonio
12:30 - 2:00 pm     Lunch (including Best Paper Award announcement)
2:00 - 3:00 pm       Special Session 2 - Challenges and Promises of Nano and Bio Communication Networks
Session Chair: Amlan Ganguly
2:00 – 2:20 pm       S2.1 - Non-classical Nanoscale On-Chip Interconnect Networks: Where We Are And Where We Need To Go
Christof Teuscher
Department of Electrical and Computer Engineering - Portland State University
2:20 – 2:40 pm       S2.2 - Synthetic Bio-Circuits: Components, Signaling, Reliability Issues
Cristian Grecu
2:40 – 3:00 pm        S2.3 - Pattern Formation Of Distributed Synthetic Bionetworks: From Local Rules To Global Behaviors
Ting Lu
Wyss Institute for Biologically Inspired Engineering - Harvard University
3:00 - 4:00 pm       Poster Session (along with coffee break)
Every paper presented during the day will have an accompanying poster.
4:00 - 5:00 pm       Market place (Demonstration session)
Session Chair: Simon Hollis

XMOS XMP-64 Demonstration
James Hanlon

Dynamic Power Management of Voltage-Frequency Island Partitioned Networks-on-Chip using Intel Sing-Chip Cloud Computer
Radu David; Paul Bogdan; Radu Marculescu; Umit Ogras

A Software Framework for Trace Analysis Targeting Multicore Platforms Design
Guopeng (Daniel) Wei; Paul Bogdan; Radu Marculescu

Reconfiguration of a 3GPP-LTE telecommunication application on a 23-core NoC-based System-on-Chip
Fabien Clermidy

A Comphrehensive Networks-on-Chip Simulator for Error Control Explorations
Qiaoyan Yu; Meilin Zhang; Paul Ampadu

NoCs Simulation Framework for OMNeT++
Yaniv Ben-Itzhak; Eitan Zahavi; Israel Cidon; Avinoam Kolodny

Spidergon STNoC Design Flow
Florentine Dubois; Jose Cano; Marcello Coppola; Jose Flich; Frederic Petrot
5:00 - 5:15 pm       Closing Remarks

technical_program.txt · Last modified: 2011/06/18 19:29 by radud     Back to top