T2: Adaptive Multi-core SoCs: Trends, Challenges and Perspectives

François Pêcheux (UPMC/LIP6, France), Gilles Sassatelli (LIRMM, France), Fabien Clermidy (CEA/LETI, France)

1:30PM - 3:30PM

Abstract: Multi-core on a single chip has become the de-facto standard in most embedded systems. These extreme high performance platforms are taking full advantage of very advanced technologies (< 32 nm node) thanks to high integration densities: the perspective of integrating hundreds/thousands of processors for fully reconfigurable platforms is in the scope. In such a context, new challenges arise: exploding applications diversity and complexity with time-changing workloads, some applications being unknown at design-time; technology spatial and temporal variabilities. In such a context, systems must be adaptive to both their external as well as internal modifications. In this tutorial, we propose to show three perspectives on the use of adaptive systems. The first one addresses the problem of booting a possibly damaged many-cores system. The second proposes a dynamic allocation strategy of both processing (CPUs) and communication (NoC) resources resulting from real-time system monitoring. Finally, the third adaptable system proposes a global dynamic power optimization for real-time applications.

Speaker Bios: François Pêcheux is working as a researcher in the LIP6/ALSoC Team and is responsible for the SystemC training activities at UPMC/LIP6 and for the development of digital models. He participates to several French and European projects and coordinates the french ANR ADAM (Adaptive Dynamic Architecture for MP2SoC) project. He also plays an active role in the development of optimized TLM models. He is the responsible for OSCI-AMS Working Group at UPMC. From 1995 to 2002 François Pêcheux has been with the “Laboratoire de Physique et Applications des Semiconducteurs” in Strasbourg, France. He also joined the “Ecole Nationale Supérieure de Strasbourg” (ENSPS) as an Associate Professor. In September 2002, he joined the LIP6 Laboratory Integrated Systems Department at the UPMC. He is the author or co-author of multiple articles and conference contributions on (SystemCbased) IC design methodology for homogeneous and heterogeneous MPSoC systems. He has introduced a new course at UPMC dedicated to modelling and simulation of heterogeneous digitally assisted systems.

Gilles Sassatelli obtained his Ph.D. thesis in electrical engineering in 2002. He then joined the group of microelectronic systems at the Darmstadt University of Technology, Germany. He is currently senior scientist at LIRMM, a joint research unit between CNRS and the University of Montpellier II. He conducts his research in the area of adaptive multiprocessor architectures in the flexible and reconfigurable computing group that he leads. Most of his research activities are conducted in collaboration with a number of international partners through collaborative projects (FP6, FP7, ENIAC, ANR, etc.) He has published over 130 publications in a number of renowned international conferences and journals, and regularly serves as track or topic chair in the major conferences in the area of reconfigurable computing (IEEE FPL, IEEE Reconfig, Worldcomp ERSA, etc.).

Fabien Clermidy obtained his Masters degree in 1994 and his Ph.D in Engineering Science in 1999 on fault-tolerant architectures. He then started working at the Center for Atomic Energy (CEA) in Saclay (near Paris) in 2000 as a research engineer. In this position, he participated in the design of a massively parallel and reconfigurable computer, with fault-tolerant features. He then moved to Grenoble and became the main architect of the Network-on-Chip activity at the microelectronic laboratory (LETI) of CEA. He then managed the MAGALI project in the design department of the LETI. MAGALI is a complex NoC-based System-on-Chip aiming to provide a prototyping platform for Software Defined Radio (SDR) and Cognitive Radio (CR) applications, with low-power features. He is currently the LETI project leader for the P2012 project, a joined ST/CEA initiative for developing multi-core architectures. Fabien Clermidy has published more than 50 papers in international conferences and journals including ISSCC, JSSC, Symposium on VLSI circuits, NOCS and DATE, and is the main inventor or co-inventor of 9 patents.

 
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