We are delighted to announce our two very exciting keynote speakers for NOCS 2011:
Anant Agarwal, Professor of Electrical Engineering and Computer Science, MIT, and Founder and CTO, Tilera Corporation
Abstract: The multicore movement has changed the face of computing. The same movement has also changed the way we look at on-chip interconnect because it is a key determinant of the performance, power efficiency and programmability of multicores. This talk will describe the architecture of a Tile Processor, a new class of multicore processor sporting on-chip mesh interconnect and coherent distributed caches targeted at embedded and cloud computing. The talk will also discuss how modern computing environments and scaling to hundreds of cores impose new requirements on multicores and their interconnect that are related to protection, virtualization, locality management, and cache coherence.
Speaker Bio: Anant Agarwal is a professor of Electrical Engineering and Computer Science at MIT and a member of CSAIL. He leads the Carbon group which focuses on research involving operating systems and architectures for manycores and clouds. He is also a founder and CTO of Tilera Corporation which created the Tile multicore processor. Agarwal holds a Ph.D. from Stanford and a bachelor's from IIT Madras. He led the development of Raw - an early tiled multicore processor, Sparcle - an early multithreaded microprocessor, and Alewife - a scalable multiprocessor. He also led the VirtualWires project at MIT and was the founder of Virtual Machine Works, which took the VirtualWires technology to market. Agarwal won the Maurice Wilkes prize for computer architecture, and MIT's Smullin and Jamieson prizes for teaching. He holds a Guinness World Record for the largest microphone array based on Raw, and is an author of the textbook “Foundations of Analog and Digital Electronic Circuits.”
Tryggve Fossum, Director of Microarchitecture Development, Intel
Abstract: Chip level integration is a driving force in the computer industry. With multi-core designs, we are integrating the network along with the processors. This changes the nature of processor communication, with dramatic improvements in bandwidth and latency. It enables new features and levels of performance. But integration complicates critical issues like power management and memory bandwidth. In this talk, we consider how moving the interconnects on die can impact the design of components like cores, cache hierarchy, memory, and parallel software. In return, the network architecture itself is impacted by integration. We will review some current on die interconnect architectures and speculate about what form they may take in the future.
Speaker Bio: Tryggve Fossum has worked as a computer architect at DEC, Compaq, and Intel, contributing to several computer designs, including the first VAX and the last Alpha, as well as Itanium and Xeon. He has a PhD from the University of Illinois and an undergraduate degree from the University of Oslo, Norway. He currently leads an advanced development team in multi core processor design.