All Embedded Systems Publications

2013

  • Z. Qian, D.-C. Juan, P. Bogdan, C.-Y. Tsui, D. Marculescu, R. Marculescu, "SVR-NoC: A Performance Analysis Tool for Network-on-Chip Architectures Using Learning-based Support Vector Regression Model," in Proc. IEEE/ACM Design, Automation, and Test in Europe Conference (DATE), Grenoble, France, March 2013.
  • H. Matsutani, P. Bogdan, R. Marculescu, Y. Take, D. Sasaki, H. Zhang, M. Koibuchi, T. Kuroda, H. Amano, ' A Case for Wireless 3D NoCs for CMPs', in Proc. ASP-DAC, Yokohama, Japan, Jan. 2013. (Best Paper Award)

  • 2012


  • S. Hollis, C. Jackson, P. Bogdan, R. Marculescu, ' Exploiting Emergence in On-chip Interconnects', in IEEE Transactions on Computers, Nov. 2012.
  • Z. Qian, P. Bogdan, G. Wei, CY. Tsui, R. Marculescu, ' A traffic-aware adaptive routing algorithm on a highly reconfigurable network-on-chip architecture', in Proc. 11th IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis (CODES+ISSS), 2012. (Best Paper Award)
  • P. Bogdan, R. Marculescu, S. Jain, R.T. Gavila, ' An Optimal Control Approach to Power Management for Multi-Voltage and Frequency Islands Multiprocessor Platforms under Highly Variable Workloads,', in Proc. of Sixth IEEE/ACM International Symposium on Networks on Chip (NOCS), pp.35,42, Copenhagen, Denmark, May, 2012. (Best Paper Award)

  • 2011

  • C.-L. Chou, R. Marculescu, U. Ogras, S. Chatterjee, M. Kishinevsky, and D. Loukianov, ' System Interconnect Design Exploration for Embedded MPSoCs', in Proc. of 2011 13th International Workshop on System Level Interconnect Prediction (SLIP), pp.1-8, June 5, 2011.
  • R. David, P. Bogdan, R. Marculescu, and U. Ogras, ' Dynamic Power Management of Voltage-Frequency Island Partitioned Networks-on-Chip Using Intel's Single-chip Cloud Computer', in Proc. of Fifth IEEE/ACM International Symposium on Networks on Chip (NOCS), pp.257-258, Pittsburgh, PA, 1-4 May 2011.
  • R. David, P. Bogdan, R. Marculescu, and U. Ogras, ' Dynamic Power Management of Voltage-Frequency Island Partitioned Networks-on-Chip Using Intel's Single-chip Cloud Computer', in Proc. of Fifth IEEE/ACM International Symposium on Networks on Chip (NOCS), pp.257-258, Pittsburgh, PA, 1-4 May 2011.
  • G. Wei, P. Bogdan, and R. Marculescu, ' A Software Framework for Trace Analysis Targeting Multicore Platforms Design', in Proc. of 2011 Fifth IEEE/ACM International Symposium on Networks on Chip (NOCS), pp.259-260, Pittsburgh, PA, 1-4 May 2011.
  • P. Bogdan, R. Marculescu. 'Non-Stationary Traffic Analysis and Its Implications on Multicore Platform Design', in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol.30, no.4, pp.508-519, April 2011.
  • C.-L. Chou and R. Marculescu,' FARM: Fault-Aware Resource Management in NoC-based Multiprocessor Platforms ', in Proc. of Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.1-6, 14-18 March 2011.
  • P. Pande, F. Clermidy, D. Puschini, I. Mansouri, P. Bogdan, R. Marculescu, and A. Ganguly, ' Sustainability Through Massively Integrated Computing: Are We Ready to Break the Energy Efficiency Wall for Single-Chip Platforms?', in Proc. of Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.1-6, 14-18 March 2011.
  • C.-L. Chou and R. Marculescu,' FARM: Fault-Aware Resource Management in NoC-based Multiprocessor Platforms ', in Proc. of Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.1-6, 14-18 March 2011.

  • 2010

  • C.-L. Chou, R. Marculescu,' Designing Heterogeneous Embedded Network-on-Chip Platforms With Users in Mind ', in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, Issues. 9, pp. 1301 - 1314, Sep. 2010.
  • P. Bogdan, R. Marculescu, ' Workload Characterization and Its impact on Multicore Platform Design', Proc. 8th IEEE/ACM/IFIP International Conference on Hardware/software codesign and system synthesis (CODES+ISSS), 2010.
  • S. Garg, D. Marculescu, and R. Marculescu, ' Custom Feedback Control: Enabling Truly Scalable On-Chip Power Management for MPSoCs', in Proc. ACM/IEEE Intl. Symposium on Low Power Electronics and Design, Austin, TX, Aug. 2010.
  • P. Bogdan, M. Kas, R. Marculescu, O. Mutlu, ' QuaLe: A Quantum-Leap Inspired Model for Non-stationary Analysis of NoC Traffic in Chip Multi-processors', in Fourth ACM/IEEE International Symposium on International Symposium on Networks-on-Chip (NOCS), 2010, Grenoble, May 2010.
  • U. Y. Ogras, P. Bogdan, R. Marculescu. 'An analytical approach for network-on-chip performance analysis', in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, Issue 12, Dec. 2010.
  • C.-L. Chou, R. Marculescu,' Run-Time Task Allocation Considering User Behavior in Embedded Multiprocessor Networks-on-Chip ', in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, no. 1, pp. 78-91, Jan. 2010.

  • 2009

  • P. Bogdan, R. Marculescu, 'Statistical Physics Approaches for Network-on-Chip Traffic Characterization', Proc. 7th IEEE/ACM International Conference on Hardware/software codesign and system synthesis (CODES/ISSS), 2009.
  • C.-L. Chou, R. Marculescu, ' User-Centric Design Space Exploration for Heterogeneous Network-on-Chip Platforms', in Proc. Design, Automation and Test in Europe Conf., Nice, France, April 2009.
  • U. Y. Ogras, R. Marculescu, D. Marculescu, E. G. Jung, ' Design and Management of Voltage-Frequency Island Partitioned Networks-on-Chip ', in IEEE Trans. on Very Large Scale Integration Systems, vol. 17, no. 3, pp. 330-341, March 2009. (Best Paper Award)
  • R. Marculescu, P. Bogdan, ' The Chip Is the Network: Toward a Science of Network-on-Chip Design', Foundations and Trends in Electronic Design Automation, vol. 2, no. 4, pp. 371-461, March 2009.
  • R. Marculescu, U. Y. Ogras, L.-S. Peh, N. E. Jerger, Y. Hoskote, ' Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives ', in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 28, no. 1, pp. 3-21, Jan. 2009.

  • 2008

  • C.-L. Chou, U. Y. Ogras, R. Marculescu,' Energy- and Performance-aware Incremental Mapping for Networks-on-Chip with Multiple Voltage Levels ', in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 27, no. 10, pp. 1866-1879, Oct. 2008.
  • C.-L. Chou, R. Marculescu, ' Contention-aware Application Mapping for Network-on-Chip Communication Architectures', in Proc. Intl. Conf. on Computer Design (ICCD), Lake Tahoe, CA, Oct. 2008.
  • P. Bogdan, R. Marculescu, ' Hitting Time Analysis for Stochastic Communication', in Proc. ACM Intl. Conf. on Nano-Net, Boston, Sep. 2008.
  • U. Y. Ogras, R. Marculescu, D. Marculescu, ' Variation-Adaptive Feedback Control for Networks-on-Chip with Multiple Clock Domains ', in Proc. IEEE/ACM Design Automation Conf., Anaheim, June 2008. (Best Paper Candidate)
  • C.-L. Chou, R. Marculescu, ' User-Aware Dynamic Task Allocation in Networks-on-Chip ', in Proc. Design, Automation and Test in Europe Conf., Munich, Germany, March 2008.
  • U. Y. Ogras, R. Marculescu, ' Analysis and Optimization of Prediction-based Flow Control in Networks-on-Chip ', in ACM Trans. on Design Automation of Electronic Systems (TODAES), vol. 13, no.1, Jan. 2008.

  • 2007

  • P. Bogdan, R. Marculescu, 'Quantum-like effects in network-on-chip buffers behavior', in Proc. 44th annual Design Automation Conference (DAC '07), New York, NY, 2007.
  • C.-L. Chou, R. Marculescu, ' Incremental Run-time Application Mapping for Homogeneous NoCs with Multiple Voltage Levels ', in Proc. CODES+ISSS, Salzburg, Austria, Oct. 2007.
  • U. Y. Ogras, R. Marculescu, H. G. Lee, P. Choudhary, D. Marculescu, M. Kaufman, P. Nelson, ' NoC Prototyping Using FPGAs: Challenges and Promising Results in NoC Prototyping Using FPGAs ', in IEEE Micro Special Issue on Interconnects for Multi-Core Chips, September/October 2007.
  • H. G. Lee, N. Chang, U. Y. Ogras, R. Marculescu, ' On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches ', in ACM Trans. on Design Automation of Electronic Systems (TODAES), Vol.12, No.3, Aug. 2007.
  • P. Bogdan, R. Marculescu, 'Quantum-like effects in network-on-chip buffers behavior', in Proc. IEEE/ACM Design Automation Conf., San Diego, June 2007.
  • U. Y. Ogras, R. Marculescu, P. Choudhary, D. Marculescu, ' Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip ', in Proc. IEEE/ACM Design Automation Conf., San Diego, June 2007.
  • C. Grecu, A. Ivanov, P. Pande, A. Jantsch, E. Salminen, U. Ogras, R. Marculescu, ' Towards Open Network-on-Chip Benchmarks ', in Proc. of First Intl. Symp. on Networks-on-Chip (NOCS'07), pp.205, May 2007.
  • U. Y. Ogras, R. Marculescu, ' Analytical Router Modeling for Networks-on-Chip Performance Analysis ', in Proc. Design, Automation and Test in Europe Conf., Nice, France, April 2007.
  • T.-C. Huang, U. Y. Ogras, R. Marculescu, ' Virtual Channels Planning for Networks-on-Chip ', in Proc. 8th International Symposium on Quality Electronic Design (ISQED'07), San Jose, March 2007.
  • P. Bogdan, T. Dumitras, R. Marculescu, ' Stochastic Communication: A New Paradigm for Fault-Tolerant Networks-on-Chip ', in Hindawi VLSI Design, Special Issue on Networks-on-Chip, Feb. 2007.
  • N. Zamora, X. Hu, R. Marculescu, ' System-Level Performance/Power Analysis for Platform-Based Design of Multimedia Applications, ' in ACM Trans. on Design Automation of Electronic Systems (TODAES), Vol.12, No.1, Jan. 2007.

  • 2006

  • J. Hu, U. Y. Ogras, R. Marculescu, ' System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design' , in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol.25, No.12, pp. 2919-2933, Dec. 2006.
  • U. Y. Ogras, R. Marculescu, ' "It’s a small world after all": NoC Performance Optimization via Long-range Link Insertion, ' in IEEE Trans. on Very Large Scale Integration Systems, Special Section on Hardware/Software Codesign and System Synthesis, Vol.14, No.7, July 2006.
  • U. Y. Ogras, R. Marculescu, 'Communication-based Design for Nanoscale SOCs,' VLSI Handbook, Wai-Kai Chen (ed.), Second Edition, CRC Book Press, December 2006.
  • P. Bogdan, R. Marculescu, ' A Theoretical Framework for On-Chip Stochastic Communication Analysis', in Proc. IEEE Intl. Conf. on Nano-Networks, Lausanne, Switzerland, Sep. 2006.
  • Y. Liu, S. Chakraborty, R. Marculescu, ' Generalized Rate Analysis for Media-Processing Platforms', 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), Sydney, August 2006.
  • R. Marculescu, U. Y. Ogras, N. H. Zamora, ' Computation and Communication Refinement for Multiprocessor SoC Design: A System-Level Perspective , ' in ACM Trans. on Design Automation of Electronic Systems, Special Issue on Novel Paradigms in System-Level Design, Vol.11, No.3, pp. 564-592, July, 2006.
  • H. G. Lee, U. Y. Ogras, R. Marculescu, N. Chang, ' Design Space Exploration and Prototyping for On-chip Multimedia Applications ', in Proc. IEEE/ACM Design Automation Conf., San Francisco, July 2006.
  • U. Y. Ogras, R. Marculescu, ' Prediction-based Flow Control for Network-on-Chip Traffic ', in Proc. IEEE/ACM Design Automation Conf., San Francisco, July 2006.
  • U. Y. Ogras, R. Marculescu, H. G. Lee, N. Chang, ' Communication Architecture Optimization: Making the Shortest Path Shorter in Regular Networks-on-Chip ', in Proc. Design, Automation and Test in Europe Conf., Munich, Germany, March 2006.
  • R. Marculescu, J. Rabaey, A. Sangiovanni-Vincentelli, ' Is "Network" The Next "Big Idea" In Design?', in Proc. Design, Automation and Test in Europe Conf., Munich, Germany, March 2006. (Hot Topic “Is “Network” The Next “Big Idea” In Design? Network Paradigms in Systems, Sensors, & Silicon”)

  • 2005

  • U. Y. Ogras, R. Marculescu, ' Application-Specific Network-on-Chip Architecture Customization via Long-Range Link Insertion', in Proc. IEEE/ACM Intl. Conf. on Computer Aided Design, San Jose, CA, Nov. 2005.
  • U. Y. Ogras, J. Hu, R. Marculescu, ' Key Research Problems in NoC Design: A Holistic Perspective ', in Proc. CODES+ISSS, Jersey City, NJ, Sep. 2005.
  • J. Hu, R. Marculescu, ' Communication and Task Scheduling of Application-Specific Networks-on-Chip', in IEE Proceedings Computers & Digital Techniques, Sep. 2005.
  • J. Hu, R. Marculescu, ' Energy- and Performance-Aware Mapping for Regular NoC Architectures', in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol.24, No.4, April 2005.
  • U. Y. Ogras, R. Marculescu, ' Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach ', in Proc. Design, Automation and Test in Europe Conf., Munich, Germany, March 2005.
  • Z. Ren, B.H. Krogh, R. Marculescu, ' Hierarchical Adaptive Dynamic Power Management ', in IEEE Trans. on Computers, Vol.54, No.4, April 2005.

  • 2004

  • J. Hu, R. Marculescu, 'Application Specific Buffer Space Allocation for Networks on Chip Router Design', in Proc. IEEE/ACM Intl. Conf. on Computer Aided Design, San Jose, CA, Nov. 2004.
  • R. Marculescu, D. Marculescu, L. Pileggi, 'Toward an Integrated Design Methodology for Fault-Tolerant, Multiple Clock/Voltage Integrated Systems', in Proc. IEEE Intl. Conf. on Compter Design (ICCD), San Jose, Ca, Oct. 2004. (Invited Paper)
  • J. Hu, Y. Shin, N. Dhanwada, R. Marculescu, 'Architecting Voltage Islands in Core-based System-on-a-Chip Designs', in Proc. ISLPED, Newport Beach, Ca, Aug. 2004.
  • J. Hu, R. Marculescu, 'DyAD - Smart Routing for Networks-on-Chip', in Proc. IEEE/ACM Design Automation Conf., San Diego, Ca, June 2004.
  • Z. Ren, B. Krogh, R.Marculescu, 'Hierarchical Adaptive Dynamic Power Management ', in Proc. Design, Automation and Test in Europe Conf., Paris, France, Feb. 2004.
  • J. Hu, R. Marculescu, 'Energy-Aware Communication and Task Scheduling for Network-on-Chip Architectures under Real-Time Constraints', in Proc. Design, Automation and Test in Europe Conf., Paris, France, Feb. 2004.
  • R. Marculescu, M. Pedram, J. Henkel, 'Distributed Multimedia System Design: A Holistic Perspective', in Proc. Design, Automation and Test in Europe Conf., Paris, France, Feb. 2004. (Special Day in Multimedia)
  • T. Dumitras, S. Kerner, R. Marculescu, 'Enabling On-Chip Diversity Through Architectural Communication Design', in Proc. ASP-DAC, Yokohama, Japan, Jan. 2004.
  • G. Varatkar, R. Marculescu, ' On-chip Traffic Modeling and Synthesis for MPEG-2 Video Applications', in IEEE Trans. on Very Large Scale Integration Systems, Vol.12, No.1, Jan. 2004. (Best Paper Award)

  • 2003

  • G. Varatkar, R. Marculescu, 'Communication-Aware Task Scheduling and Voltage Selection for Total Systems Energy Minimization', in Proc. IEEE/ACM Intl. Conf. on Computer Aided Design, San Jose, CA, Nov. 2003.
  • T. Dumitras, R. Marculescu, 'On-Chip Stochastic Communication,' in Proc. Design, Automation and Test in Europe Conf., Munich, Germany, March 2003.
  • J. Hu, R. Marculescu, 'Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures', in Proc. Design, Automation and Test in Europe Conf., Munich, Germany, March 2003. (Best Paper Award)
  • J. Hu, R. Marculescu, 'Energy-Aware Mapping for Tile-based NOC Architectures Under Performance Constraints', in Proc. ASP-DAC, Kitakyushu, Japan, Jan. 2003.
  • T. Dumitras, S. Kerner, R. Marculescu, 'Towards on-chip fault-tolerant communication', in Proc. ASP-DAC, Kitakyushu, Japan, Jan. 2003. (Best Paper Award)

  • 2002

  • G. Varatkar, R. Marculescu, 'On-Chip Communication Analysis for Multimedia Applications', in Proc. IEEE Intl. Conf. on Multimedia and Expo, Lausanne, Switzerland, Aug. 2002.
  • G. Varatkar, R. Marculescu, 'Traffic Analysis for On-chip Networks Design of Multimedia Applications' , in Proc. IEEE/ACM Design Automation Conf., New Orleans, LA, June 2002.
  • J. Hu, Y. Deng, R. Marculescu, 'System-Level Point-to-Point Communication Synthesis Using Floorplanning Information', in Proc. ASP-DAC, Bangalore, India, Jan. 2002.
  • D. Marculescu and R. Marculescu, 'System and microarchitectural level power modeling, optimization, and their implications in energy aware computing,' in Power Aware Design Methodologies, M. Pedram, J. Rabaey (eds.), Kluwer Academic Publishers, 2002.

  • 2001

  • R. Marculescu, A. Nandi, L. Lavagno, A. Sangiovanni-Vincentelli, 'System-Level Power/Performance Analysis of Portable Multimedia Systems Communicating over Wireless Channels' , in Proc. IEEE/ACM Intl. Conf. on Computer Aided Design, San Jose, CA, Nov. 2001.
  • A. Nandi, R. Marculescu, 'System-Level Power/Performance Analysis for Embedded Systems Design' , in Proc. IEEE/ACM Design Automation Conf., Las Vegas, NV, June 2001.
  • R. Marculescu, A. Nandi, 'Probabilistic Application Modeling for System-Level Performance Analysis' , in Proc. Design, Automation and Test in Europe Conf., Munich, Germany, March 2001. (Best Paper Award)