18-745 Class Project:

Improving Performance through Data Object Fusion

Shelley Chen Nikos Hardavellas

Carnegie Mellon University

Department of Electrical and Computer Engineering

Pittsburgh, PA 15213

{shelleychen, nhardavellas}@cmu.edu

Overview:

Technological advancements in semiconductor fabrication, coupled with architectural innovation, have resulted in lighting-speed improvements in processor performance which doubles every eighteen months. While memory capacity has increased commensurately with processor performance, memory access speeds improve at the glacial rate of almost 10% annually [9]. The memory wall is rising fast, and promotes memory reference behavior to the dominant factor determining overall performance of many important applications (e.g., commercial database systems spend 25% to 50% of their execution time waiting at the memory system [10]). To alleviate this problem we propose object fusion, a compile time technique that co-locates elements of a pointer-based data structure which are likely to be accessed contemporaneously, and re-orders their fields to improve cache line utilization during traversal.

Proposal [pdf] [ps] [html]

Milestone [pdf] [ps] [html]

Final [pdf] [ps] [html]

Related Research Papers:

[1] J. Rao, K. A. Ross. "Cache Conscious Indexing for Decision-Support in Main Memory." In Proceedings of the 25^th VLDB, 1999.

[2] S. Chen, P. B. Gibbons, T. C. Mowry. "Improving Index Performance through Prefetching." In Proceedings of the SIGMOD 2001 Conference, May 2001.

[3] T. M. Chilimbi, J. R. Larus. "Using generational garbage collection to implement cache-conscious data placement." In Proceedings of the 1998 International Symposium on Memory Management, October 1997.

[4] T. M. Chilimbi, B. Davidson, J. R. Larus. "Cache-Conscious Structure Definition." In Proceedings of the ACM SIGPLAN '99 Conference on Programming Language Design and Implementation, May 1999.

[5] D. Troung, F. Bodin, A. Seznic. "Improving cache behavior of dynamically allocated data structures." In International Conference of Parallel Architectures and Compilation Techniques, October 1998.

[6] T. M. Chilimbi, M. D. Hill, J. R. Larus. "Cache Conscious Structure Layout." In Proceedings of the ACM SIGPLAN ?99 Conference on Programming Language Design and Implementation, May 1999.

[7] T. M. Chilimbi. "Efficient Representations and Abstractions for Quantifying and Exploiting Data Reference Locality." In Proceedings of the ACM SIGPLAN?01 Conference on Programming Language Design and Implementation, June 2001.

[8] D. Kroft. "Lockup-free instruction fetch/prefetch cache organization." In Proceedings of 8^th Annual International Symposium on Computer Architecture, May 1981.

[9] D. A. Patterson, T. Anderson, N. Cardwell, R. Fromm, K. Keaton, C. Kozyrakis, R. Thomas, K Yelick. "A case for intelligent RAM." In IEEE Micro, pp. 34-44, April 1997

[10] A. Ailamaki, D. J. DeWitt, M. D. Hill, D. A. Wood. "DBMSs on a Modern Processor: Where Does Time Go?" In Proceedings of VLDB Conference, 1999.

[11] C-K. Luk, T. Mowry. "Compiler-based prefetching for recursive data structures." In Proceedings of 7^th International Conference on Architectural Support for Programming Languages and Operating Systems, October 1996.

[12] A. J. Smith. "Cache Memories." In ACM Computing Surveys, 14(3):473-530, 1982.

[13] M. V. Wilkes. "Slave memories and dynamic storage allocation." In IEEE Transactions on Electronic Computers, pp. 270-271, April 1965.

[14] D. Callahan, K. Kennedy, A. Poterfield. "Software Prefetching." In Proceedings of the 4^th International Conference on Architectural Support for Programming Languages and Operating Systems, April 1991.