Qian Yu

Ph.D.

OFFICE ADDRESS:   Hamerschlag Hall A-313, 5000 Forbes Avenue / Pittsburgh, PA 15213

PHONE NUMBERS: ( 412 ) 268– 7920

EMAIL ADDRESS:  qianyu(at)ece.cmu.edu

OBJECTIVE:

To apply a post-doctor position in Computer Engineering

EXPERTISE:

· Switching Network Design in Real-Time Supercomputer;

· Micro-architecture Research of DSP Microprocessor;

· VLSI System Design and Verification.

EDUCATION:

July 2006     Ph.D. E.E. Chinese Academy of Sciences                                      Beijing, China

                       Major: VLSI System Design                  GPA: 4.0

                       Dissertation Title: "Research and Design of Simultaneous Multithreading Micro-architecture"

July 2001     B.S. E.E. University of Science and Technology of China Hefei, China

                       Major: Communication Engineering       GPA: 3.9

                       Thesis Title: "Investigation of DSP Datapath on Altera CPLD"

EXPERIENCE:

University of Illinois at Urbana-Champaign                                                                  Urbana, IL USA

Supervisor: Luddy Harrison, Associate Professor of University of Illinois at Urbana-Champaign

Research of ILLIAC6 Supercomputer                                                             Jan. 2007-present

        Controlled and coordinated the progress of developing communication protocol stack. The main

work included clarifying the hardware/software interface and each layer's specification, analyzing and

optimizing datapath for bandwidth, allocating global resource of device, and building up a run-time

reconfigurable solution. The whole protocol stack has almost been finished and expected to be verified

on mezzanine card soon.
        Designed the crossbar switches in the protocol stack. Crossbar switch interacts with both physical

channels and the software mapper. Changed with software scheduling, crossbar switches varied from

static routing, round-robin dynamic scheduling and fixed-length packet time-slot interchanger. The first

one fits only light overload. The second one avoids the NP-problem in static routing but provides

unpredictable bandwidth. The final version is capable to guarantee tight bandwidth for real-time

application. Crossbar switch design has been tested on development board in 200MHz frequency and

supplied up to 6.4 Gbps for each link.

　

Chinese Academy of Sciences                                                                                                Beijing, China

Advisor: Chaohuan Hou, Academician of Chinese Academy of Sciences, IEEE fellow

Research of Processor's Micro-architecture                                                Mar. 2005-Jul. 2006

          Designed and evaluated Asymmetrical SMT (Simultaneous Multithreading) micro-architecture based on a

VLIW microprocessor. Asymmetrical SMT executes the highest-priority thread as the ideal foreground routine,

while the system throughput and power efficiency  (the ratio of instructions to power per second) were increased

by utilizing thread-level parallelism.  The experiment results show that 4-thread asymmetric SMT architecture

can work in the same frequency as one-thread VLIW core, getting over 3 times IPC and 1.56 times power

efficiency with 34% area overhead.

The Design of High Performance DSP&CPU Microprocessor                  Oct. 2002-Mar. 2005

           Designed a VLIW microprocessor which supported by national basic research program of China. Duties

included: 1) Implemented the control path of the microprocessor in RTL level; 2) Accomplished the custom

design of 16-ports write-through  register file in transistor-level, which supported 4-issued microprocessor;

3) Verified the function on both simulation and formal methods. Many assembly programs  with sub-word

parallelism were created to verify the function of SIMD coprocessor. The chip was designed in 0.18μm CMOS

technology with over one million gates.

PUBLICATIONS:

*Q. Yu, C.H. Hou, et al., "Fast Implementation of 2D DCT Based on Media Instructions", Computer

Engineering, Dec. 2007.
*Q. Yu, C.H. Hou, et al., "Custom Design of 16-port Write-Through Memory Cell", Microelectronic and

Computers, Dec. 2006
*Q. Yu, C.H. Hou, et al., "A Design of 6-Port CMOS Register File", Micro- electronic and Computers,

Nov. 2005.
*Q. Yu, C.H. Hou, et al., "A Design of 500MHz 10-Read 6-Write Register File", in Proceedings. 6th

International Conference on ASIC, Oct. 2005.
*Q. Yu, and D.H. Wang, "A Design of Regularized Multiplier Generator", in Proceedings. 5th Inter-

national Conference on ASIC, Oct. 2003.

COMPUTER STILLS:

Program Language: RTL Verilog and VHDL, Assembly language, C++, Matlab

Design tools: Synopsys, Mentor, HSPICE, Xilinx

COURSES:

VLSI Design;                                  Digital System Engineering;                  Computer Architecture;

Signal and System;                        Communication Theory.

AWARDS AND HONORS:

+Excellent Graduate Student Scholarship, Graduate University of Chinese Academy of Sciences

+The Excellent Graduated Student of EE department, University of Science and Technology of China

LANGUAGE:

Chinese /English bilingual