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Journal Papers:
[1]
Q. Yu, Y. Shao, T.J. Zhang, D.H. Wang, W. Li, "Fast Implementation of 2D DCT
Based on Media Instructions", Computer Engineering, Jul. 2007. Accepted
for publication
[2] Q. Yu, D.H. Wang, T.J. Zhang, and C.H. Hou, "Custom Design of 16-port
Write-Through Memory Cell", Microelectronic and Computers, Dec. 2006.
Accepted for publication.
[3] Q. Yu, D.H. Wang, T.J. Zhang, and C.H. Hou, "A Design of 6-Port CMOS
Register File", Microelectronic and Computers, pp.37-40, Nov. 2005.
Conference Papers:
[1]
Y. X. Zheng, J. Li, J. Liu, and Q. Yu, "Automatic Within-Pair-Skew
Compensation for 6.25Gbps Differential Links Using Wide-Bandwidth Delay Units",
in Proceedings IEEE International Symposium on Circuits and Systems, May
2006, pp. 2121-2124.
[2] Q. Yu, D.H. Wang, T.J. Zhang, and C.H. Hou, "A Design of 500MHz
10-Read 6-Write Register File", in Proceedings. 6th International Conference
on ASIC, Oct. 2005, pp.266-269.
[3] Y. Shao, Q. Yu, T.J. Zhang, R. Shan, and C.H. Hou, "A New HW/SW
Co-design Methodology to Generate a System Level Platform Based on LISA", in
Proceedings. 6th International Conference on ASIC, Oct. 2005, pp.215-218.
[4] D.H. Wang, Q. Yu, Y. Liu, "Area optimization in Deep Sub-micro VLSI
Design", in Proceedings. 6th International Conference on ASIC, Oct. 2005,
pp.800-803.
[5] D.H. Wang, Q. Yu, Y. Hong, and C.H. Hou, "SuperV back-end design flow
based on Astro", in IEEE International Symposium on Communications and
Information Technology, Oct. 2005, pp.1524 - 1527.
[6] Q. Yu, and D.H. Wang, "A Design of Regularized Multiplier Generator",
in Proceedings. 5th International Conference on ASIC, Oct. 2003, pp.1269
- 1272.
[7] R. Shan, Y. Hong, D.H. Wang, T.J. Zhang, Q. Yu, and C.H. Hou, "A
32-bit Hybrid Microprocessor Design for Multimedia Applications", in
Proceedings. 5th International Conference on ASIC, Oct. 2003, pp.385 - 388.
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