Publications

Accurate and Complexity-Effective Spatial Pattern Prediction
Chi F. Chen, Se-Hyun Yang, Babak Falsafi, and Andreas Moshovos
In the Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA), February 2004
postscript, PDF.

Power-Aware High-Performance Cache Memories
Se-Hyun Yang
Ph.D. Thesis, Carnegie Mellon University, December 2003
PDF.

Near-Optimal Bitline Precharging in High-Performance Nanoscale CMOS Caches
Se-Hyun Yang and Babak Falsafi
In the Proceedings of the 36th Annual ACM/IEEE International Symposium on Microarchitecture (MICRO-36), December 2003
postscript, PDF.

Accurate and Complexity-Effective Spatial Pattern Prediction
Chi F. Chen
M.S. Thesis, Carnegie Mellon University, August 2003
PDF.

Performance and Energy Trade-offs of Bitline Isolation in Nanoscale CMOS Caches
Se-Hyun Yang and Babak Falsafi
Workshop on Complexity-Effective Design (WCED) held in conjunction with the 30th International Symposium on Computer Architecture (ISCA-30), June 2003.

Practical Voltage-Scaling for Fixed-Priority RT-Systems
Saowanee Saewong and Ragunathan Rajkumar
In Proceedings of the ninth IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), May 2003
gzipped postscript.

Gated Precharging: Using Temporal Locality of Subarrays to Save Deep-Submicron Cache Energy
Se-Hyun Yang and Babak Falsafi
Workshop on Complexity-Effective Design (WCED) held in conjunction with the 29th International Symposium on Computer Architecture (ISCA-29), May 2002

Analysis of Hierarchical Fixed-Priority Scheduling
Saowanee Saewong, Ragunathan Rajkumar, John P. Lehoczky, Mark H. Klein
In proceedings of the IEEE Euromicro Conference on Real-Time Systems, June 2002
gzipped postscript.

Optimal Static Voltage-Scaling for Real-Time Systems
Saowanee Saewong and Ragunathan Rajkumar
Submitted for publication, May 2002
gzipped postscript.

Practical Voltage Scaling for Power-Aware Real-Time Systems
Saowanee Saewong and Ragunathan Rajkumar
Submitted for publication, April 2002
gzipped postscript.

Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay
Se-Hyun Yang, Michael D. Powell, Babak Falsafi, and T. N. Vijaykumar
IEEE International Symposium on High Performance Computer Architecture (HPCA), February 2002
postscript, PDF.

Resource Sharing in Reservation-Based Systems
Dionisio de Niz, Luca Abeni, Saowanee Saewong and Ragunathan Rajkumar
In Proceedings of the IEEE Real-Time Systems Symposium, December 2001
gzipped postscript.

Evaluating Opportunity and Effectiveness of Cache Resizing to Reduce Energy Dissipation
Se-Hyun Yang, Michael D. Powell, Babak Falsafi, Kaushik Roy, and T. N. Vijaykumar
CACLM Technical Report #2001-001, Carnegie Mellon University, June 2001
postscript, PDF.

An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches
Se-Hyun Yang, Michael D. Powell, Babak Falsafi, Kaushik Roy, and T. N. Vijaykumar
IEEE International Symposium on High Performance Computer Architecture (HPCA), Janunary 2001
postscript, PDF.

An Energy-Efficient High-Performance Deep-Submicron Instruction Cache
Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy, and T. N. Vijaykumar
IEEE Transactions on VLSI, special issue on Low-Power Electronics and Design, February 2001
postscript, PDF.

JETTY: Filtering Snoops for Reduced Power Consumption in SMP Servers
Andreas Moshovos, Gokhan Memik, Babak Falsafi, and Alok Choudhary
ACM/IEEE International Symposium on High-Performance Computer Architecture (HPCA), January 2001
postscript, PDF.