Carnegie Mellon University



Jeyanandh Paramesh

Assistant Professor

RF/Mixed-Signal IC Design

2117 Hammerschlag Hall
Carnegie Mellon University
5000 Forbes Avenue
Pittsburgh, PA 15213

Phone: 412-268-1290

E-mail: paramesh@ece.cmu.edu


University of Washington, Seattle, Ph.D, Electrical Engineering, 2006
Oregon State University, Corvallis M.S, Electrical Engineering, 1998
Indian Institute of Technology, Madras
 B.Tech, Electrical Engineering, 1996

Biosketch   Teaching   Publications    Honors

Biosketch

Jeyanandh Paramesh is  Assistant Professor of Electrical and Computer Engineering at Carnegie-Mellon University. He has held product development positions with Analog Devices, where he designed high-performance data converters, and Motorola as an analog and RF integrated circuit designer for cellphone transceivers. Most recently, he was a researcher with the Communications Circuit Lab, Intel where he developed multi-antenna receivers, transmitters and high-speed data converters for next-generation wireless computer networks.
    His current research interests include high-frequency analog and RF circuit integrated circuits and data converters in silicon technologies. He is also interested in the design of analog circuits that use digital signal processing algorithms to assist and enhance their performance.


Teaching

Spring 2005 EE 538 RF Integrated Circuit Design (University of Washington)
Spring 2007
ECE 321  Analysis and Design of Analog Integrated Circuits
Fall 2007
 ECE 721 Advanced Analog Integrated Circuits


Journal Publications

  1.  J. Paramesh and A. von Jouanne, “Use of sigma-delta modulation to control EMI from switch-mode power supplies,” IEEE Transactions on Industrial Electronics, vol. 48,  Feb. 2001, pp.111 - 117. [paper]
  2. D.J. Allstot, S. Aniruddhan, M. Chu, J. Paramesh and S. Shekhar, “Recent advances and design trends in CMOS radio frequency integrated circuits,” International Journal of High Speed Electronics and Systems, June 2005. [paper]
  3. J. Paramesh, R. Bishop, K. Soumyanath and D.J. Allstot, “A four-antenna receiver in 90nm CMOS for beamforming and spatial diversity,” IEEE J. Solid-State Circuits, vol. 40, pp. 2515-2524, Dec. 2005. [paper]
  4. M. Elmala, J. Paramesh and K. Soumyanath,, "A 90nm Doherty power amplifier in 90nm CMOS with minumum AM-PM distortion," IEEE J. Solid-State Circuits, vol. 41, pp. 1323-1332, Jun. 2006.  [paper]
  5. J. Paramesh and D.J. Allstot, “Analysis of the Bridged T-coil Circuit Using the Extra-Element Theorem,”  IEEE Transactions on Circuits and Systems II: Express Briefs, pp. 1408 - 1412, Dec 2006.  [paper]
  6. Y. Tang, S. Gupta, K. Chang, J. Paramesh and D. J. Allstot, "A Cascaded Complex ADC with Digital I/Q Mismatch Calibration," Accepted for publication to IEEE Transactions on Circuits and Systems I: Regular Papers.

Conference Publications

  1. J. Paramesh and A. von Jouanne, “A Use of  S-D modulation to control EMI in switch-mode power supplies”, IEEE Applied Power Electronics Conference and Exposition,  vol. 1 , pp. 14-18, March 1999.  [paper]
  2. S. Dow, B. Ballweber, Ling-Miao Chou, D. Eickbusch, J. Irwin, G. Kurtzman, P. Manapragada, D. Moeller, J. Paramesh, G. Black, R. Wollscheid, K. Johnson,  “A dual-band direct conversion transceiver IC for GSM/DCS”,  Digest of Technical Papers, IEEE International Solid-State Circuits Conference, vol. 1 , 3-7, pp. 230-231, 462, Feb 2002. [paper] [slides]
  3. X. Li, D. Ozis, J. Paramesh, H. Zarei and D. J. Allstot, “A 10-GHz smart antenna receiver in 0.25um SiGe BiCMOS technology”, Semiconductor Research Corporation Techcon, Sept. 2003.
  4. X. Li, D. Ozis, J. Paramesh, H. Zarei and D. J. Allstot, “Circuit blocks for multiple-antenna receivers”, IEEE Workshop on Wireless Circuits and Systems, pp. 43-44, May 2004.
  5. J. Paramesh, R.Bishop, K. Soumyanath and D. Allstot, “ A 1.4V, 5GHz four-antenna cartesian-combining receiver in 90nm CMOS for beamforming and spatial diversity applications”, Digest of Technical Papers, IEEE International Solid-State Circuits Conference, pp. 210-211, 594, Feb 2005. [paper]  [slides]
  6. D. J. Allstot, G. Banerjee, M. Chu, J. Paramesh, X. Li, S. Shekhar and K. Soumyanath, “Circuit techniques for CMOS multiple-antenna transceivers,” IEEE Radio-Frequency Integrated Circuits Conference, pp. 225-228, 2005. (Invited) [pdf]
  7. D. Ozis, J. Paramesh and D. J. Allstot, “Analysis and Design of Lumped-element Quadrature Couplers with Lossy Passive Elements,” IEEE International Symposium on Circuits and Systems, 2006. [paper]
  8. J. Paramesh, R. Bishop, K. Soumyanath and D. J. Allstot, “A 1.4V 11b 330MHz S-D ADC for next-generation WLAN,”  Digest of Technical Papers, IEEE VLSI Circuits Symposium pp. 196-197, 2003.  [paper] [slides]
  9.  D.J. Allstot, C.T. Charles, S. Kodali, X. Li, D. Ozis, J. Paramesh, S. Shekhar, and J.S. Walling, “CMOS integrated transformers: coming of age,” IEEE Intl. Conf. on Solid-State and Integrated Circuit Technology, Oct. 2006, pp. 1480-1483. (Invited) [paper]
  10. D. Ozis, J. Paramesh and D. J. Allstot, "A CMOS 5GHz image-reject receiver front-end architecture," IEEE Radio-frequency Integrated Circuits Symposium (RFIC), pp 321-324, 2007. [paper]
  11. Y. Tang, S. Gupta, J. Paramesh and D. J. Allstot, "A digital-summing feedforward S-D modulator and its application to a cascade ADC." IEEE International Symposium on Circuits and Systems, pp. 485-488, 2007. [paper]

Honors

1997  Chevron Engineering Scholarship
2003  Intel Foundation Doctoral Fellowship
2005  Analog Devices Outstanding Student Designer Award