Tools
Discrete Fourier Transform IP Generator
The Spiral DFT IP Generator, (v1.1, released November 2005) generates highly-parameterized synthesizable Verilog cores for computing the Discrete Fourier Transform. The generator is web-based, and generates Verilog dynamically.
The user controls various parameters, including the degree of parallelism, which allows him or her to specify the desired tradeoff between cost and performance. Additionally, the user can control the balance between slices (general FPGA cells) and block RAMs (dedicated on-chip memory).
Spiral for Hardware: From Math to Efficient Datapath
Given an algorithm as a formula and high-level hardware design decisions, we generate tradeoff-balanced hardware implementations in RTL Verilog. This work is an extension of the DFT Generator above, and allows us to generate a wider range of DFT implementations (across various algorithms, architectural options, radices, and target platforms). See Technical Report CSSI 2007-01 by following the "Research" link in the menu to your left for more information.
Streaming Data Permutations
Given a permutation and a desired throughput, we generate an efficient streaming implementation, suitable for FPGA or VLSI. The resulting implementation uses a small number of RAMs and interconnect networks. For an important subset of problems, our solutions are provably optimal in certain cost metrics. Submitted for publication.
Benchmark
Incorporating the results from the tools listed above, we produce a wide range of flexible implementations of the discrete Fourier transform. Here, we show a representative performance/area plot, wherein we compare our generated cores with designs from Xilinx's LogiCore Library (ver. 3.2).
All results compiled with Xilinx ISE ver. 8.2i, and are targeted for the Xilinx XC2VP100 FPGA.
Please click to view graph.
