8:30-8:45 |
Opening Remarks |
8:45-10:00 |
Keynote Address Intel Labs |
10:00-10:20 |
Break |
10:20-11:50 |
Microarchitecture-
& Circuit-Level Techniques An Optimized Front-End Physical
Register File with Banking and Writeback Filtering Reducing Delay and Power Consumption of the Wakeup Logic through
Instruction Packing and Tag Memoization Bit-Sliced Datapath for
Energy-Efficient High Performance Microprocessors Sumeet Kumar, Prateek Pujara,
Eren Kursun, Glenn Reinman,
Suleyman Sair, Anahita Shayesteh, Tim Sherwood |
11:50-1:00 |
Lunch |
1:00-2:20 |
Power-Aware
Memory & Interconnect Systems Co-operative
Software-Hardware Power Management for Main Memory Hai Huang, Kang Shin, Charles
Lefurgy, Karthick Rajamani, Tom Keller, Eric Hensbergen, Freeman Rawson Energy-Aware
Data Prefetching for General-Purpose Programs Bus Power
Estimation and Power-Efficient Bus Arbitration for System-on-a-Chip Embedded
Processors Ke Ning, David Kaeli Context-independent
Codes for Off-Chip Interconnects Kartik Mohanram, |
|
Break |
2:40-4:00 |
Frequency-/Voltage-Scaling
Techniques Dynamic
Processor Throttling for Power Efficient Computations Effective
Dynamic Voltage Scaling through CPU-boundness Detection Chung-Hsing Hsu, Wu-Chun Feng Safe
Overprovisioning: Using Power Limits to Increase Aggregate Throughput Mark Femal, Power
Consumption Breakdown on Modern Laptop Aqeel Mahesri, |
4:00 |
Discussion & Closing Remarks |