CMU MEMS Laboratory Publication Abstract

 

in IEEE Design & Test Magazine, pp. 18-27, October 1999.
Hierarchical Design and Test of Integrated Microsystems
T. Mukherjee, G. Fedder and S. Blanton
ABSTRACT:
The advent of monolithic integration of mechanical structures with electronics has ushered an era in which microchips can sense and act as well as compute and communicate. The complex device, component and system design issues involving such integrated chips requires the development of new CAD representations, methodologies and tools. A suite of tools that simultaneously considers the mechanical and electromechanical nature in such microsystems with traditional electronics natures is presented. These tools are based on a design methodology that partitions the micromechanical and electromechanical components in a hierarchical fashion into low-level reusable elements. This mixed-domain circuit representation is combined with Kirchhoffian network theory for an integrated microsystem simulation environment. Behavioral models from this hierarchical representation are combined with optimization into a tool that generates microstructure layouts meeting specified performance criteria. A feature-recognition based extractor translates layout geometry into the mixed-domain circuit representation, enabling layout verification. Models that integrate the effects of process contaminations on a microstructure form the basis of a MEMS testing methodology.
© 1999 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Full paper (PDF) (opens in new window).


This page was generated in 0.030568 seconds at 03:59:18 am EST on 22 Nov 2017.

overview | projects | people | publications | intranet | resources         © 1998-2009  Carnegie Mellon