|CMU MEMS Laboratory Publication Abstract|
|in M.S. Thesis, May 1998, Carnegie Mellon University, Pittsburgh, PA.|
|Design and Simulation of A CMOS-MEMS Accelerometer|
| With the development of MicroElectroMechanicalSystems (MEMS), inertial instruments have seen significant progress over the past decades. The advantages of low-cost, low-power, small size, batch fabrication makes MEMS-based inertial sensors have a wide range of applications in automotive, consumer, computer, and navigation markets. As the most mature MEMS-based inertial sensor application, current MEMS accelerometers have the highest degree of integration, with sensing elements and electronic interface circuitry on a single chip.
In a conventional polysilicon surface micromachining process, microaccelerometers are made from custom processes combining polysilicon surface micromachining and electronic circuits processes. Microstructures are separated from electronics by around 100mm due to process limitations, which wastes significant amount of silicon area. Parasitic capacitance between the structural layer to the substrate can be around 50 pF for a typical inertial sensor design. Interconnection between microstructures and electronics is implemented by the polysilicon layer or by diffusion with large resistance and parasitic capacitance to substrate, which result in large wiring noise and signal attenuation. Extra micromachining process steps usually involve performance and yield compromises, and are incompatible with standard IC technology.
The accelerometer described in this report is designed with the CMOS-MEMS technology developed at Carnegie Mellon. The process flow, shown in Figure 1.1, incorporates microstructures with the Hewlett-Packard 0.5mm three-metal n-well CMOS process. After the foundry CMOS processing, two steps of dry etches, with the top metal layer as etch resistant mask, are performed to create microstructures. An anisotropic reactive ion etch (RIE) with CHF 3 /O 2 is first performed to etch away exposed oxides, and form microstructural sidewalls. This step is followed by a more isotropic RIE with SF 6 /O 2 to etch bulk silicon and release the microstructures from substrate. Dry etches eliminate sticking problems associated with competing wet-etch release processes.
Comparatively, CMOS-MEMS technology has many advantages over polysilicon surface micromachining processes. Compatibility with conventional CMOS technology enables fast, repeatable, reliable, and economical fabrication of MEMS devices integrated with conventional CMOS. Microstructures can be integrated as close as 12 mm from on-chip electronics limited by the silicon undercuts. Since the mask metal layer is defined by lithography in the CMOS process, the minimum microstructure feature size is 1.5mm and scales with CMOS technology. Structural layers are released with a gap of about 20 mm above the substrate, providing a much smaller parasitic capacitance to the substrate. Aluminum interconnect eliminates thermal noise caused by wiring resistance. Multiple conductors can be built into structural layers, which allow novel and flexible design, such as fully differential capacitive sensors, self-actuating springs and gimbaled gyroscope designs. Such designs can not be implemented in homogeneous conducting structural layers such as those in polysilicon technology.
In this report, design issues are addressed with the emphasis on exploiting advantages and benefits provided by CMOS-MEMS technology, and overcoming potential difficulties.
|© 1998 Carnegie Mellon University, Department of Electrical and Computer Engineering.|
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