CMU MEMS Laboratory Publication Abstract


in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE), pp. 279-280, March 7-11, 2005, Munich, Germany.
Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters
Y. T. Chien, D. Chen, J. H. Lou, G. K. Ma, R. A. Rutenbar and T. Mukherjee
This paper suggests a practical “hybrid” synthesis methodology which integrates designer-derived analytical models for system-level description with simulation-based models at the circuit level. We show how to optimize stage-resolution to minimize the power in a pipelined ADC. Exploration (via detailed synthesis) of several ADC configurations is used to show that a 4-3-2… resolution distribution uses the least power for a 13-bit 40 MSPS converter in a 0.25 μm CMOS process.
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Full paper (PDF) (opens in new window).

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