CMU MEMS Laboratory Publication Abstract


in Proceedings of the IEEE 1995 Custom Integrated Circuits Conference (CICC), pp. 543-546, May 1-4, 1995, Santa Clara, CA, USA.
High-speed Low-Power Integrating CMOS Sample-and-Hold Amplifier Architecture
R. Carley and T. Mukherjee
A novel “current-mode ” Jumpling architecture for sample-and-hold (S&H) ampli$ers results in a substantial reduction in error due to sampling clock jitter and aperture time. These reduced errors make possible a substantial reduction in power over a conventional “voltage-mode ” S&H with the same sample rate. In order to demonstrate the pegormance of this architecture, a S&H with 4 subsampled parallel outputs has been designed using less than 2mm2 die area in a 1 . 2μ C MOS process. Operating at 100 MS/s the circuit dissipates only 25mW of power. Integral nonlinearity of the S&H circuit is less than 0.4%. Simulation results of the second generation S&H circuit with improved common-mode rejection will also be presented.
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