CMU MEMS Laboratory Publication Abstract


in Proceedings of the IEEE 1990 Custom Integrated Circuits Conference (CICC), pp. 8.5.1-4, May 13-16, 1990, Boston, MA, USA.
Rapid Yield Estimation as a Computer Aid for Analog Circuit Design
T. Mukherjee and R. Carley
A rapid yield estimation methodology that aids the analog circuit designer in making design tradeoffs that improve yield is presented. ARYE (Analog Rapid Yield Estimator), a CAD tool that implements this methodology for op amps has been incorporated into ACACIA, the CMU Analog Design System, in order to allow analog designers to quickly explore the impact of design changes on yield. A design example using ARYE and ACACIA to enhance the yield of a two-stage op amp design will be presented.
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Full paper (PDF) (opens in new window).

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