CMU MEMS Laboratory Publication Abstract

 

in Technical Proceedings of the Fourth International Conference on Modeling and Simulation of Microsystems (MSM), pp. 108-111, March 19-21, 2001, Hilton Head, SC, USA.
Challenges in CMOS-MEMS Extraction
B. Baidya and T. Mukherjee
ABSTRACT:
CMOS micromachining processes are being increasingly used to fabricate integrated MEMS devices. Verification of such designs requires extraction from layout to mixed domain circuits and MEMS schematics for lumped parameter simulation. The higher etch hole density and multilayer interconnect in CMOSMEMS designs results in a larger and more complex problem than in polysilicon MEMS. In addition, integrated MEMS verification needs accurate extraction of mechanical and electrical parasitics. This paper reports an extractor with improved scanline based algorithms to meet the larger problem size associated with integrated CMOS MEMS layouts. In addition, a hierarchical bin representation is used to store the multilayer electrical connectivity information. A new graph based algorithm, which reads in an user customizable library file, is used to recognize the wide range of comb drive and spring designs resulting from the flexibility in connectivity. The utility of the extractor is demonstrated using selected designs.
© 2001 Computational Publications. Abstracting is permitted with credit to the source. Other copying, reprint or repoduction requests should be addressed to: Copyrights Manager, Computational Publications, Copyright Office, 899 Rue Jean de Gingins, 01220 Divonne les Bains, France. Computational Publications is a subsuduary of the Applied Computational Researh Society, a non-profit organization
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